Disable interrupts and do some refactoring.

patches/reboot.s

@@ -54,13 +54,16 @@ payload_maxsize equ 0x10000   ; Maximum size for the payload (maximum that CakeB
         movne r4, #0
         bne read_payload ; Go read the real payload.
 
-    ; Copy the last digits of the wanted firm to the 5th byte of the payload
-    add r2, sp, #0x3A8 - 0x70
-    ldr r0, [r2, #0x27]
-    ldr r1, =payload_addr + 4
-    str r0, [r1]
-    ldr r0, [r2, #0x2B]
-    str r0, [r1, #4]
+    ; Copy the low TID (in UTF-16) of the wanted firm to the 5th byte of the payload
+    add r0, sp, #0x3A8 - 0x70
+    add r0, 0x1A
+    add r1, r0, #0x10
+    ldr r2, =payload_addr + 4
+    copy_TID_low:
+        ldrh r3, [r0], #2
+        strh r3, [r2], #2
+        cmp r0, r1
+        blo copy_TID_low
 
     ; Set kernel state
     mov r0, #0

source/firm.c

@@ -36,6 +36,8 @@
 #include "i2c.h"
 #include "../build/injector.h"
 
+extern u16 launchedFirmTIDLow[8]; //defined in start.s
+
 static firmHeader *const firm = (firmHeader *)0x24000000;
 static const firmSectionHeader *section;
 
@@ -76,14 +78,14 @@ void main(void)
     needConfig = fileRead(&config, configPath) ? MODIFY_CONFIGURATION : CREATE_CONFIGURATION;
 
     //Determine if this is a firmlaunch boot
-    if(*(vu8 *)0x23F00005)
+    if(launchedFirmTIDLow[5] != 0)
     {
         if(needConfig == CREATE_CONFIGURATION) mcuReboot();
 
         isFirmlaunch = true;
 
         //'0' = NATIVE_FIRM, '1' = TWL_FIRM, '2' = AGB_FIRM
-        firmType = *(vu8 *)0x23F00009 == '3' ? SAFE_FIRM : (FirmwareType)(*(vu8 *)0x23F00005 - '0');
+        firmType = launchedFirmTIDLow[7] == u'3' ? SAFE_FIRM : (FirmwareType)(launchedFirmTIDLow[5] - u'0');
 
         nandType = (FirmwareSource)BOOTCONFIG(0, 3);
         firmSource = (FirmwareSource)BOOTCONFIG(2, 1);

source/start.s

@@ -26,12 +26,19 @@
 _start:
     b start
 
-    .word 0, 0
+.global launchedFirmTIDLow
+launchedFirmTIDLow:
+    .hword 0, 0, 0, 0, 0, 0, 0, 0 
 
 start:
     @ Change the stack pointer
     mov sp, #0x27000000
 
+    @ Disable interrupts
+    mrs r0, cpsr
+    orr r0, #0x1C0
+    msr cpsr_cx, r0
+
     @ Disable caches / MPU
     mrc p15, 0, r0, c1, c0, 0  @ read control register
     bic r0, #(1<<12)           @ - instruction cache disable