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208 lines
14 KiB
C
208 lines
14 KiB
C
#pragma once
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/*
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* This file is part of open_agb_firm
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* Copyright (C) 2021 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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// Based on SD specification version 8.00.
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#include "drivers/tmio.h"
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// Controller specific macros. Add controller specific bits here.
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// SD_[command type]_[response type]_[transfer type]
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// Command type: CMD = regular command, ACMD = Application-Specific Command.
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// Transfer type: R = read, W = write.
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#define SD_CMD_NONE(id) (CMD_RESP_NONE | (id))
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#define SD_CMD_R1(id) (CMD_RESP_R1 | (id))
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#define SD_CMD_R1b(id) (CMD_RESP_R1b | (id))
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#define SD_CMD_R2(id) (CMD_RESP_R2 | (id))
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#define SD_CMD_R6(id) (CMD_RESP_R6 | (id))
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#define SD_CMD_R7(id) (CMD_RESP_R7 | (id))
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#define SD_CMD_R1_R(id) (CMD_DATA_R | CMD_DATA_EN | CMD_RESP_R1 | (id))
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#define SD_CMD_R1_W(id) (CMD_DATA_W | CMD_DATA_EN | CMD_RESP_R1 | (id))
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#define SD_ACMD_R1(id) (CMD_RESP_R1 | CMD_ACMD | (id))
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#define SD_ACMD_R3(id) (CMD_RESP_R3 | CMD_ACMD | (id))
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#define SD_ACMD_R1_R(id) (CMD_DATA_R | CMD_DATA_EN | CMD_RESP_R1 | CMD_ACMD | (id))
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// Basic Commands (class 0).
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#define SD_GO_IDLE_STATE SD_CMD_NONE(0u) // -, [31:0] stuff bits.
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#define SD_ALL_SEND_CID SD_CMD_R2(2u) // R2, [31:0] stuff bits.
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#define SD_SEND_RELATIVE_ADDR SD_CMD_R6(3u) // R6, [31:0] stuff bits.
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#define SD_SET_DSR SD_CMD_NONE(4u) // -, [31:16] DSR [15:0] stuff bits.
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#define SD_SELECT_CARD SD_CMD_R1b(7u) // R1b, [31:16] RCA [15:0] stuff bits.
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#define SD_DESELECT_CARD SD_CMD_NONE(7u) // -, [31:16] RCA [15:0] stuff bits.
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#define SD_SEND_IF_COND SD_CMD_R7(8u) // R7, [31:12] reserved bits [11:8] supply voltage (VHS) [7:0] check pattern.
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#define SD_SEND_CSD SD_CMD_R2(9u) // R2, [31:16] RCA [15:0] stuff bits.
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#define SD_SEND_CID SD_CMD_R2(10u) // R2, [31:16] RCA [15:0] stuff bits.
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#define SD_VOLTAGE_SWITCH SD_CMD_R1(11u) // R1, [31:0] reserved bits (all 0).
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#define SD_STOP_TRANSMISSION SD_CMD_R1b(12u) // R1b, [31:0] stuff bits.
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#define SD_SEND_STATUS SD_CMD_R1(13u) // R1, [31:16] RCA [15] Send Task Status Register [14:0] stuff bits.
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#define SD_SEND_TASK_STATUS SD_CMD_R1(13u) // R1, [31:16] RCA [15] Send Task Status Register [14:0] stuff bits.
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#define SD_GO_INACTIVE_STATE SD_CMD_NONE(15u) // -, [31:16] RCA [15:0] reserved bits.
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// Block-Oriented Read Commands (class 2).
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#define SD_SET_BLOCKLEN SD_CMD_R1(16u) // R1, [31:0] block length.
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#define SD_READ_SINGLE_BLOCK SD_CMD_R1_R(17u) // R1, [31:0] data address.
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#define SD_READ_MULTIPLE_BLOCK SD_CMD_R1_R(18u) // R1, [31:0] data address.
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#define SD_SEND_TUNING_BLOCK SD_CMD_R1_R(19u) // R1, [31:0] reserved bits (all 0).
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#define SD_SPEED_CLASS_CONTROL SD_CMD_R1b(20u) // R1b, [31:28] Speed Class Control [27:0] See command description.
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#define SD_ADDRESS_EXTENSION SD_CMD_R1(22u) // R1, [31:6] reserved bits (all 0) [5:0] extended address.
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#define SD_SET_BLOCK_COUNT SD_CMD_R1(23u) // R1, [31:0] Block Count.
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// Block-Oriented Write Commands (class 4).
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// SET_BLOCKLEN
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// SPEED_CLASS_CONTROL
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// ADDRESS_EXTENSION
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// SET_BLOCK_COUNT
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#define SD_WRITE_BLOCK SD_CMD_R1_W(24u) // R1, [31:0] data address.
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#define SD_WRITE_MULTIPLE_BLOCK SD_CMD_R1_W(25u) // R1, [31:0] data address.
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#define SD_PROGRAM_CSD SD_CMD_R1_W(27u) // R1, [31:0] stuff bits.
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// Block Oriented Write Protection Commands (class 6).
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#define SD_SET_WRITE_PROT SD_CMD_R1b(28u) // R1b, [31:0] data address.
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#define SD_CLR_WRITE_PROT SD_CMD_R1b(29u) // R1b, [31:0] data address.
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#define SD_SEND_WRITE_PROT SD_CMD_R1_R(30u) // R1, [31:0] write protect data address.
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// Erase Commands (class 5).
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#define SD_ERASE_WR_BLK_START SD_CMD_R1(32u) // R1, [31:0] data address.
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#define SD_ERASE_WR_BLK_END SD_CMD_R1(33u) // R1, [31:0] data address.
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#define SD_ERASE SD_CMD_R1b(38u) // R1b, [31:0] Erase Function.
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// Lock Card (class 7).
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// SET_BLOCKLEN
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// Command 40 "Defined by DPS Spec.".
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#define SD_LOCK_UNLOCK SD_CMD_R1_W(42u) // R1, [31:0] Reserved bits (Set all 0).
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// Application-Specific Commands (class 8).
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#define SD_APP_CMD SD_CMD_R1(55u) // R1, [31:16] RCA [15:0] stuff bits.
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#define SD_GEN_CMD_R SD_CMD_R1_R(56u) // R1, [31:1] stuff bits. [0]: RD/WR = 1.
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#define SD_GEN_CMD_W SD_CMD_R1_W(56u) // R1, [31:1] stuff bits. [0]: RD/WR = 0.
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// Application Specific Commands used/reserved by SD Memory Card.
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#define SD_APP_SET_BUS_WIDTH SD_ACMD_R1(6u) // R1, [31:2] stuff bits [1:0] bus width.
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#define SD_APP_SD_STATUS SD_ACMD_R1_R(13u) // R1, [31:0] stuff bits.
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#define SD_APP_SEND_NUM_WR_BLOCKS SD_ACMD_R1_R(22u) // R1, [31:0] stuff bits.
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#define SD_APP_SET_WR_BLK_ERASE_COUNT SD_ACMD_R1(23u) // R1, [31:23] stuff bits [22:0] Number of blocks.
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#define SD_APP_SD_SEND_OP_COND SD_ACMD_R3(41u) // R3, [31] reserved bit [30] HCS (OCR[30]) [29] reserved for eSD [28] XPC [27:25] reserved bits [24] S18R [23:0] VDD Voltage Window (OCR[23:0]).
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#define SD_APP_SET_CLR_CARD_DETECT SD_ACMD_R1(42u) // R1, [31:1] stuff bits [0] set_cd.
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#define SD_APP_SEND_SCR SD_ACMD_R1_R(51u) // R1, [31:0] stuff bits.
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// Switch Function Commands (class 10).
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#define SD_SWITCH_FUNC SD_CMD_R1_R(6u) // R1, [31] Mode 0: Check function 1: Switch function [30:24] reserved (All '0') [23:20] reserved for function group 6 (0h or Fh) [19:16] reserved for function group 5 (0h or Fh) [15:12] function group 4 for PowerLimit [11:8] function group 3 for Drive Strength [7:4] function group 2 for Command System [3:0] function group 1 for Access Mode.
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// Function Extension Commands (class 11).
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#define SD_READ_EXTR_SINGLE SD_CMD_R1_R(48u) // R1, [31] MIO0: Memory, 1: I/O [30:27] FNO[26] Reserved (=0) [25:9] ADDR [8:0] LEN.
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#define SD_WRITE_EXTR_SINGLE SD_CMD_R1_W(49u) // R1, [31] MIO0: Memory, 1: I/O [30:27] FNO [26] MW [25:9] ADDR [8:0] LEN/MASK.
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#define SD_READ_EXTR_MULTI SD_CMD_R1_R(58u) // R1, [31] MIO0: Memory, 1: I/O [30:27] FNO [26] BUS0: 512B, 1: 32KB [25:9] ADDR [8:0] BUC.
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#define SD_WRITE_EXTR_MULTI SD_CMD_R1_W(59u) // R1, [31] MIO0: Memory, 1: I/O [30:27] FNO [26] BUS0: 512B, 1: 32KB [25:9] ADDR [8:0] BUC.
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// Command Queue Function Commands (class 1).
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#define SD_Q_MANAGEMENT SD_CMD_R1b(43u) // R1b, [31:21] Reserved [20:16]: Task ID [3:0]: Operation Code (Abort tasks etc.).
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#define SD_Q_TASK_INFO_A SD_CMD_R1(44u) // R1, [31] Reserved [30] Direction [29:24] Extended Address [23] Priority [22:21] Reserved [20:16] Task ID [15:0] Number of Blocks.
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#define SD_Q_TASK_INFO_B SD_CMD_R1(45u) // R1, [31:0] Start block address.
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#define SD_Q_RD_TASK SD_CMD_R1_R(46u) // R1, [31:21] Reserved [20:16] Task ID [15:0] Reserved.
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#define SD_Q_WR_TASK SD_CMD_R1_W(47u) // R1, [31:21] Reserved [20:16] Task ID [15:0] Reserved.
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// 4.10.1 Card Status.
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// Type:
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// E: Error bit.
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// S: Status bit.
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// R: Detected and set for the actual command response.
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// X: Detected and set during command execution. The host can get the status by issuing a command with R1 response.
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//
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// Clear Condition:
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// A: According to the card current status.
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// B: Always related to the previous command. Reception of a valid command will clear it (with a delay of one command).
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// C: Clear by read.
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#define SD_R1_AKE_SEQ_ERROR (1u<<3) // E R C, Error in the sequence of the authentication process.
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#define SD_R1_APP_CMD (1u<<5) // S R C, The card will expect ACMD, or an indication that the command has been interpreted as ACMD.
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#define SD_R1_FX_EVENT (1u<<6) // S X A, ExtensionFunctions may set this bit to get host to deal with events.
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#define SD_R1_READY_FOR_DATA (1u<<8) // S X A, Corresponds to buffer empty signaling on the bus.
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#define SD_R1_STATE_IDLE (0u<<9) // S X B
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#define SD_R1_STATE_READY (1u<<9) // S X B
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#define SD_R1_STATE_IDENT (2u<<9) // S X B
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#define SD_R1_STATE_STBY (3u<<9) // S X B
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#define SD_R1_STATE_TRAN (4u<<9) // S X B
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#define SD_R1_STATE_DATA (5u<<9) // S X B
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#define SD_R1_STATE_RCV (6u<<9) // S X B
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#define SD_R1_STATE_PRG (7u<<9) // S X B
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#define SD_R1_STATE_DIS (8u<<9) // S X B
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#define SD_R1_ERASE_RESET (1u<<13) // S R C, An erase sequence was cleared before executing because an out of erase sequence command was received.
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#define SD_R1_CARD_ECC_DISABLED (1u<<14) // S X A, The command has been executed without using the internal ECC.
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#define SD_R1_WP_ERASE_SKIP (1u<<15) // E R X C, Set when only partial address space was erased due to existing write protected blocks or the temporary or permanent write protected cardwas erased.
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#define SD_R1_CSD_OVERWRITE (1u<<16) // E R X C, Can be either one of the following errors: -The read only section of the CSD does not match the card content. -An attempt to reverse the copy (set as original) or permanent WP (unprotected) bits was made.
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// 17 reserved for DEFERRED_RESPONSE (Refer to eSD Addendum)
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#define SD_R1_ERROR (1u<<19) // E R X C, A general or an unknown error occurred during the operation.
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#define SD_R1_CC_ERROR (1u<<20) // E R X C, Internal card controller error:
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#define SD_R1_CARD_ECC_FAILED (1u<<21) // E R X C, Card internal ECC was applied but failed to correct the data.
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#define SD_R1_ILLEGAL_COMMAND (1u<<22) // E R B, Command not legal for the card state.
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#define SD_R1_COM_CRC_ERROR (1u<<23) // E R B, The CRC check of the previous command failed.
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#define SD_R1_LOCK_UNLOCK_FAILED (1u<<24) // E R X C, Set when a sequence or password error has been detected in lock/unlock card command.
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#define SD_R1_CARD_IS_LOCKED (1u<<25) // S X A, When set, signals that the card is locked by the host.
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#define SD_R1_WP_VIOLATION (1u<<26) // E R X C, Set when the host attempts to write to a protected block or to thetemporary or permanent write protected card.
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#define SD_R1_ERASE_PARAM (1u<<27) // E R X C, An invalid selection of write-blocks for erase occurred.
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#define SD_R1_ERASE_SEQ_ERROR (1u<<28) // E R C, An error in the sequence of erase commands occurred.
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#define SD_R1_BLOCK_LEN_ERROR (1u<<29) // E R X C, The transferred block length is not allowed for this card, or the number of transferred bytes does not match the block length.
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#define SD_R1_ADDRESS_ERROR (1u<<30) // E R X C, A misaligned address which did not match the block length was used in the command.
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#define SD_R1_OUT_OF_RANGE (1u<<31) // E R X C, The command's argument was out of the allowed range for this card.
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#define SD_R1_ERR_ALL (SD_R1_OUT_OF_RANGE | SD_R1_ADDRESS_ERROR | SD_R1_BLOCK_LEN_ERROR | \
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SD_R1_ERASE_SEQ_ERROR | SD_R1_ERASE_PARAM | SD_R1_WP_VIOLATION | \
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SD_R1_LOCK_UNLOCK_FAILED | SD_R1_COM_CRC_ERROR | SD_R1_ILLEGAL_COMMAND | \
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SD_R1_CARD_ECC_FAILED | SD_R1_CC_ERROR | SD_R1_ERROR | \
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SD_R1_CSD_OVERWRITE | SD_R1_WP_ERASE_SKIP | SD_R1_AKE_SEQ_ERROR)
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// Argument bits for SEND_IF_COND (CMD8).
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#define SD_CMD8_CHK_PATT (0xAAu) // Check pattern.
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#define SD_CMD8_VHS_2_7_3_6V (1u<<8) // Voltage supplied (VHS) 2.7-3.6V.
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#define SD_CMD8_PCIe (1u<<12) // PCIe Avail-ability.
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#define SD_CMD8_PCIe_1_2V (1u<<13) // PCIe 1.2V Support.
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// 5.1 OCR register.
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#define SD_OCR_2_7_2_8V (1u<<15) // 2.7-2.8V.
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#define SD_OCR_2_8_2_9V (1u<<16) // 2.8-2.9V.
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#define SD_OCR_2_9_3_0V (1u<<17) // 2.9-3.0V.
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#define SD_OCR_3_0_3_1V (1u<<18) // 3.0-3.1V.
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#define SD_OCR_3_1_3_2V (1u<<19) // 3.1-3.2V.
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#define SD_OCR_3_2_3_3V (1u<<20) // 3.2-3.3V.
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#define SD_OCR_3_3_3_4V (1u<<21) // 3.3-3.4V.
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#define SD_OCR_3_4_3_5V (1u<<22) // 3.4-3.5V.
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#define SD_OCR_3_5_3_6V (1u<<23) // 3.5-3.6V.
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#define SD_OCR_S18A (1u<<24) // S18A: Switching to 1.8V Accepted. 0b: Continues current voltage signaling, 1b: Ready for switching signal voltage.
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#define SD_OCR_CO2T (1u<<27) // Over 2TB Card. CCS must also be 1 if this is 1.
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#define SD_OCR_UHS_II (1u<<29) // UHS-II Card Status. 0b: Non UHS-II Card, 1b: UHS-II Card.
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#define SD_OCR_CCS (1u<<30) // Card Capacity Status. 0b: SDSC, 1b: SDHC or SDXC.
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#define SD_OCR_READY (1u<<31) // Busy Status. 0b: On Initialization, 1b: Initialization Complete.
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// Argument bits for SEND_OP_COND (ACMD41).
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// For voltage bits see OCR register above.
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#define SD_ACMD41_S18R (1u<<24) // S18R: Switching to 1.8V Request. 0b: Use current signal voltage, 1b: Switch to 1.8V signal voltage.
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#define SD_ACMD41_HO2T (1u<<27) // Over 2TB Supported Host. HCS must also be 1 if this is 1.
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#define SD_ACMD41_XPC (1u<<28) // SDXC Power Control. 0b: Power Saving, 1b: Maximum Performance.
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#define SD_ACMD41_HCS (1u<<30) // Host Capacity Support. 0b: SDSC Only Host, 1b: SDHC or SDXC Supported.
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// 4.3.10 Switch Function Command.
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// mode: 0 = check function, 1 = set function
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// pwr: Function group 4 Power Limit.
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// driver: Function group 3 Driver Strength.
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// cmd: Function group 2 Command system.
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// acc: Function group 1 Access mode.
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#define SD_SWITCH_FUNC_ARG(mode, pwr, driver, cmd, acc) ((mode)<<31 | 0xFFu<<16 | ((pwr)&0xFu)<<12 | ((driver)&0xFu)<<8 | ((cmd)&0xFu)<<4 | ((acc)&0xFu))
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