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256 lines
9.9 KiB
C
256 lines
9.9 KiB
C
/*
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* This file is part of open_agb_firm
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* Copyright (C) 2021 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "types.h"
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#include "mem_map.h"
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#include "fb_assert.h"
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#include "arm11/drivers/scu.h"
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#include "mmio.h"
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#include "arm.h"
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// Mem permissions. Bit 5 (APX), 1-0 (AP[1:0]), all other padding.
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#define PERM_NA (0b000000u)
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#define PERM_PRIV_RW_USR_NA (0b000001u)
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#define PERM_PRIV_RW_USR_RO (0b000010u)
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#define PERM_PRIV_RW_USR_RW (0b000011u)
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// These 2 don't work for supersections because no APX bit.
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#define PERM_PRIV_RO_USR_NA (0b100001u)
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#define PERM_PRIV_RO_USR_RO (0b100010u)
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// Predefined mem attributes. Bit 12-10 (TEX[2:0]), 1 (C), 0 (B), all other padding.
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// All of these count for outer and inner.
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#define ATTR_STRONGLY_ORDERED (0b0000000000000u) // Always shared
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#define ATTR_SHARED_DEVICE (0b0000000000001u)
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#define ATTR_NORM_WRITE_TROUGH_NO_ALLOC (0b0000000000010u) // Behaves as noncacheable on ARM11 MPCore.
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#define ATTR_NORM_WRITE_BACK_NO_ALLOC (0b0000000000011u) // Behaves as write-back write-allocate.
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#define ATTR_NORM_NONCACHABLE (0b0010000000000u)
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#define ATTR_NORM_WRITE_BACK_ALLOC (0b0010000000011u)
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#define ATTR_NONSHARED_DEVICE (0b0100000000000u)
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// Policies for custom normal memory attributes.
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#define POLI_NONCACHABLE_UNBUFFERED (0b00u)
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#define POLI_WRITE_BACK_ALLOC_BUFFERED (0b01u)
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#define POLI_WRITE_THROUGH_NO_ALLOC_BUFFERED (0b10u) // Behaves as noncacheable on ARM11 MPCore.
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#define POLI_WRITE_BACK_NO_ALLOC_BUFFERED (0b11u) // Behaves as write-back write-allocate.
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// Make custom normal memory attributes.
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#define CUSTOM_ATTR(outer, inner) (1u<<12 | (outer)<<10 | (inner))
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// Converts the attribute bits from L1 format to L2 format.
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// Required for mmuMapPages().
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#define L1_TO_L2(attr) (((attr)>>6 | (attr)) & 0x73)
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typedef struct
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{
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u32 l1[4096];
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u32 l2PrivReg[256]; // L2 table for MPCore private region
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u32 l2Axiwram[256]; // L2 table for AXIWRAM
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u32 l2Boot11[256]; // L2 table for boot11 (high vectors)
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} MmuTables;
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static MmuTables *const g_mmuTables = (MmuTables*)A11_MMU_TABLES_BASE;
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/**
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* @brief Maps up to 256 16 MiB sections of memory. Domain is always 0.
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*
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* @param[in] va The virtual address base. Must be aligned to 16 MiB.
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* @param[in] pa The physical address base. Must be aligned to 16 MiB.
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* @param[in] num The number of sections to map.
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* @param[in] access The access permission bits.
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* @param[in] xn If this memory should be marked as execute never.
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* @param[in] attr Other attribute bits like caching.
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*/
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static void mmuMapSupersections(u32 va, u32 pa, u32 num, u8 access, bool xn, u32 attr)
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{
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fb_assert(!(va & ~0xFF000000));
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fb_assert(!(pa & ~0xFF000000));
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fb_assert(num < 256);
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u32 *const l1Table = g_mmuTables->l1;
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for(u32 i = 0; i < 0x1000000 * num; i += 0x1000000)
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{
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const u32 l1Ss = (va + i)>>20;
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for(u32 n = 0; n < 16; n++)
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{
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l1Table[l1Ss + n] = (pa + i) | 1u<<18 | access<<10 | xn<<4 | attr<<2 | 0b10u;
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}
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}
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}
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/**
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* @brief Maps up to 4096 1 MiB sections of memory.
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*
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* @param[in] va The virtual address base. Must be aligned to 1 MiB.
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* @param[in] pa The physical address base. Must be aligned to 1 MiB.
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* @param[in] num The number of sections to map.
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* @param[in] shared If the sections are shared memory.
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* @param[in] access The access permission bits.
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* @param[in] domain One of the 16 possible domains.
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* @param[in] xn If this memory should be marked as execute never.
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* @param[in] attr Other attribute bits like caching.
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*/
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static void mmuMapSections(u32 va, u32 pa, u32 num, bool shared, u8 access, u8 domain, bool xn, u32 attr)
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{
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fb_assert(!(va & ~0xFFF00000));
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fb_assert(!(pa & ~0xFFF00000));
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fb_assert(num < 4096);
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u32 *const l1Table = g_mmuTables->l1;
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for(u32 i = 0; i < 0x100000 * num; i += 0x100000)
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{
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l1Table[(va + i)>>20] = (pa + i) | shared<<16 | access<<10 |
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domain<<5 | xn<<4 | attr<<2 | 0b10u;
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}
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}
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/**
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* @brief Maps up to 256 4 KiB pages of memory.
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* @brief The mapped range must not cross the next section.
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*
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* @param[in] va The virtual address base. Must be aligned to 4 KiB.
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* @param[in] pa The physical address base. Must be aligned to 4 KiB.
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* @param[in] num The number of pages to map.
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* @param l2Table The L2 MMU table address base for this mapping.
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* @param[in] shared If the pages are shared memory.
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* @param[in] access The access permission bits.
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* @param[in] domain One of the 16 possible domains.
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* @param[in] xn If this memory should be marked as execute never.
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* @param[in] attr Other attribute bits like caching.
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*/
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static void mmuMapPages(u32 va, u32 pa, u32 num, u32 *const l2Table, bool shared, u8 access, u8 domain, bool xn, u32 attr)
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{
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fb_assert(!(va & ~0xFFFFF000));
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fb_assert(!(pa & ~0xFFFFF000));
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fb_assert(num < 256);
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fb_assert(!((u32)l2Table & ~0xFFFFFC00));
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for(u32 i = 0; i < 0x1000 * num; i += 0x1000)
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{
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l2Table[(va + i)>>12 & 0xFF] = ((pa + i) & 0xFFFFF000) | shared<<10 | access<<4 | attr<<2 | 0b10u | xn;
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}
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g_mmuTables->l1[va>>20] = (u32)l2Table | domain<<5 | 0b01u;
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}
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void setupMmu(void)
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{
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// FCSE PID Register (FCSE PID = 0)
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// Note: This must be 0 before disabling the MMU otherwise UB
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__setFcsepidr(0);
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// Context ID Register (ASID = 0, PROCID = 0)
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__setCidr(0);
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// TTBR0 address shared page table walk and outer cachable write-through, no allocate on write
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__setTtbr0((u32)g_mmuTables->l1 | 0x12);
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// Use the 16 KiB L1 table only
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__setTtbcr(0);
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// Domain 0 = client, remaining domains all = no access
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__setDacr(1);
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static volatile bool syncFlag = false;
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if(!__getCpuId())
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{
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// Clear L1 and L2 tables
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iomemset((u32*)g_mmuTables, 0, sizeof(MmuTables));
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// IO mem mapping
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mmuMapSections(IO_MEM_ARM9_ARM11, IO_MEM_ARM9_ARM11, 4, true,
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PERM_PRIV_RW_USR_NA, 0, true, ATTR_SHARED_DEVICE);
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// MPCore private region mapping
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mmuMapPages(MPCORE_PRIV_REG_BASE, MPCORE_PRIV_REG_BASE, 2,
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g_mmuTables->l2PrivReg, false, PERM_PRIV_RW_USR_NA,
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0, true, L1_TO_L2(ATTR_SHARED_DEVICE));
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// VRAM mapping
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mmuMapSections(VRAM_BASE, VRAM_BASE, 6, true, PERM_PRIV_RW_USR_NA, 0,
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true, ATTR_NORM_WRITE_TROUGH_NO_ALLOC);
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// AXIWRAM core 0/1 stack mapping
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mmuMapPages(A11_C0_STACK_START, A11_C0_STACK_START, 4, g_mmuTables->l2Axiwram,
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true, PERM_PRIV_RW_USR_NA, 0, true, L1_TO_L2(ATTR_NORM_WRITE_BACK_ALLOC));
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// AXIWRAM MMU table mapping
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const u32 mmuTablesPages = ((sizeof(MmuTables) + 0xFFFu) & ~0xFFFu) / 0x1000;
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mmuMapPages((u32)g_mmuTables, (u32)g_mmuTables, mmuTablesPages, g_mmuTables->l2Axiwram, true,
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PERM_PRIV_RO_USR_NA, 0, true, L1_TO_L2(ATTR_NORM_WRITE_TROUGH_NO_ALLOC));
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extern const u32 __start__[];
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extern const u32 __text_pages__[];
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extern const u32 __rodata_start__[];
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extern const u32 __rodata_pages__[];
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extern const u32 __data_start__[];
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const u32 dataPages = (AXIWRAM_BASE + AXIWRAM_SIZE - (u32)__data_start__) / 0x1000;
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// text
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mmuMapPages((u32)__start__, (u32)__start__, (u32)__text_pages__,
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g_mmuTables->l2Axiwram, true, PERM_PRIV_RO_USR_NA, 0, false,
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L1_TO_L2(ATTR_NORM_WRITE_BACK_ALLOC));
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// rodata
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mmuMapPages((u32)__rodata_start__, (u32)__rodata_start__, (u32)__rodata_pages__,
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g_mmuTables->l2Axiwram, true, PERM_PRIV_RO_USR_NA, 0, true,
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L1_TO_L2(ATTR_NORM_WRITE_BACK_ALLOC));
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// data, bss and heap
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mmuMapPages((u32)__data_start__, (u32)__data_start__, dataPages,
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g_mmuTables->l2Axiwram, true, PERM_PRIV_RW_USR_NA, 0, true,
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L1_TO_L2(ATTR_NORM_WRITE_BACK_ALLOC));
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// FCRAM with New 3DS extension
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mmuMapSupersections(FCRAM_BASE, FCRAM_BASE, 16, PERM_PRIV_RW_USR_NA, true,
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ATTR_NORM_WRITE_BACK_ALLOC);
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// Map fastboot executable start to boot11 mirror (exception vectors)
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mmuMapPages(BOOT11_MIRROR2, (u32)__start__, 1, g_mmuTables->l2Boot11, true,
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PERM_PRIV_RO_USR_NA, 0, false, L1_TO_L2(ATTR_NORM_WRITE_BACK_ALLOC));
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// Invalidate tag RAMs before enabling SMP as recommended by the MPCore doc.
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// TODO: Disable SCU on poweroff/reboot/FIRM launch.
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Scu *const scu = getScuRegs();
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scu->ctrl = SCU_CTRL_RST_VAL; // Disable SCU and parity checking. Access to all aliases.
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scu->inval_all = SCU_WAY_ALL; // Invalidate SCU tag RAMs of all CPUs.
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scu->ctrl = SCU_CTRL_RST_VAL | SCU_EN; // Enable SCU.
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syncFlag = true;
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__sev();
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}
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else while(!syncFlag) __wfe();
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// Invalidate TLB (Unified TLB operation)
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__asm__ volatile("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
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__dsb();
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// Enable Return stack, Dynamic branch prediction, Static branch prediction,
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// Instruction folding and SMP mode: the CPU is taking part in coherency
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__setAcr(__getAcr() | 0x2F);
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// Enable MMU, D-Cache, Program flow prediction,
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// I-Cache, high exception vectors, Unaligned data access,
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// subpage AP bits disabled
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__setCr(__getCr() | 0xC03805);
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// Invalidate Both Caches. Also flushes the branch target cache
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__asm__ volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (0) : "memory");
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__dsb();
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__isb();
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}
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