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87 lines
3.4 KiB
C
87 lines
3.4 KiB
C
#pragma once
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/*
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* This file is part of open_agb_firm
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* Copyright (C) 2021 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <assert.h>
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#include "types.h"
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#include "mem_map.h"
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// Most register names from: https://github.com/torvalds/linux/blob/master/include/linux/irqchip/arm-gic.h
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#define GICC_REGS_BASE (MPCORE_PRIV_BASE + 0x100)
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#define GICD_REGS_BASE (MPCORE_PRIV_BASE + 0x1000)
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typedef struct
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{
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vu32 ctrl; // 0x00 Control Register.
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vu32 primask; // 0x04 Priority Mask Register.
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vu32 binpoint; // 0x08 Binary Point Register.
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const vu32 intack; // 0x0C Interrupt Acknowledge Register.
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vu32 eoi; // 0x10 End of Interrupt Register.
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const vu32 runningpri; // 0x14 Running Priority Register.
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const vu32 highpri; // 0x18 Highest Pending Interrupt Register.
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} Gicc;
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static_assert(offsetof(Gicc, highpri) == 0x18, "Error: Member highpri of Gicc is not at offset 0x18!");
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typedef struct
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{
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vu32 ctrl; // 0x000 Interrupt Distributor Control Register.
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const vu32 ctr; // 0x004 Interrupt Controller Type Register.
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u8 _0x8[0xf8];
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vu32 enable_set[8]; // 0x100 Interrupt Enable set Registers.
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u8 _0x120[0x60];
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vu32 enable_clear[8]; // 0x180 Interrupt Enable clear Registers.
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u8 _0x1a0[0x60];
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vu32 pending_set[8]; // 0x200 Interrupt Pending set Registers.
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u8 _0x220[0x60];
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vu32 pending_clear[8]; // 0x280 Interrupt Pending clear Registers.
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u8 _0x2a0[0x60];
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const vu32 active_set[8]; // 0x300 Interrupt Active Bit Registers.
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u8 _0x320[0xe0];
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vu32 pri[64]; // 0x400 Interrupt Priority Registers.
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u8 _0x500[0x300];
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vu32 target[64]; // 0x800 Interrupt CPU targets Registers.
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u8 _0x900[0x300];
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vu32 config[16]; // 0xC00 Interrupt Configuration Registers.
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u8 _0xc40[0xc0];
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const vu32 line_level[8]; // 0xD00 Interrupt Line Level Registers.
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u8 _0xd20[0x1e0];
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vu32 softint; // 0xF00 Software Interrupt Register.
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u8 _0xf04[0xdc];
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const vu32 periph_ident0; // 0xFE0 Periphal Identification Register 0.
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const vu32 periph_ident1; // 0xFE4 Periphal Identification Register 1.
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const vu32 periph_ident2; // 0xFE8 Periphal Identification Register 2.
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const vu32 periph_ident3; // 0xFEC Periphal Identification Register 3.
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const vu32 primecell0; // 0xFF0 PrimeCell Identification Register 0.
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const vu32 primecell1; // 0xFF4 PrimeCell Identification Register 1.
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const vu32 primecell2; // 0xFF8 PrimeCell Identification Register 2.
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const vu32 primecell3; // 0xFFC PrimeCell Identification Register 3.
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} Gicd;
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static_assert(offsetof(Gicd, primecell3) == 0xFFC, "Error: Member primecell3 of Gicd is not at offset 0xFFC!");
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ALWAYS_INLINE Gicc* getGiccRegs(void)
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{
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return (Gicc*)GICC_REGS_BASE;
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}
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ALWAYS_INLINE Gicd* getGicdRegs(void)
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{
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return (Gicd*)GICD_REGS_BASE;
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}
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