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https://gitee.com/anod/open_agb_firm.git
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147 lines
5.5 KiB
C
147 lines
5.5 KiB
C
#pragma once
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/*
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* This file is part of libn3ds
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* Copyright (C) 2024 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "types.h"
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#include "mem_map.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#define GPIO_REGS_BASE (IO_COMMON_BASE + 0x47000)
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// 3 GPIOs (bits 0-2)
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#define REG_GPIO1_DAT *((const vu8*)(GPIO_REGS_BASE + 0x00)) // Read-only.
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// 2 GPIOs (bits 0-1)
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#define REG_GPIO2 *(( vu32*)(GPIO_REGS_BASE + 0x10))
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#define REG_GPIO2_DAT *(( vu8*)(GPIO_REGS_BASE + 0x10))
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#define REG_GPIO2_DIR *(( vu8*)(GPIO_REGS_BASE + 0x11)) // 0 = input, 1 = output.
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#define REG_GPIO2_EDGE *(( vu8*)(GPIO_REGS_BASE + 0x12)) // IRQ edge 0 = falling, 1 = rising.
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#define REG_GPIO2_IRQ *(( vu8*)(GPIO_REGS_BASE + 0x13)) // 1 = IRQ enable.
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// 1 GPIO (bit 0)
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#define REG_GPIO2_DAT2 *(( vu16*)(GPIO_REGS_BASE + 0x14)) // Only bit 0 writable.
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// 12 GPIOs (bits 0-11)
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#define REG_GPIO3_H1 *(( vu32*)(GPIO_REGS_BASE + 0x20)) // First half.
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#define REG_GPIO3_DAT *(( vu16*)(GPIO_REGS_BASE + 0x20))
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#define REG_GPIO3_DIR *(( vu16*)(GPIO_REGS_BASE + 0x22))
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#define REG_GPIO3_H2 *(( vu32*)(GPIO_REGS_BASE + 0x24)) // Second half.
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#define REG_GPIO3_EDGE *(( vu16*)(GPIO_REGS_BASE + 0x24))
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#define REG_GPIO3_IRQ *(( vu16*)(GPIO_REGS_BASE + 0x26))
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// 1 GPIO (bit 0)
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#define REG_GPIO3_DAT2 *(( vu16*)(GPIO_REGS_BASE + 0x28)) // WiFi.
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#define GPIO_INPUT (0u)
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#define GPIO_OUTPUT BIT(0)
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#define GPIO_NO_IRQ (0u)
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#define GPIO_IRQ_FALLING (BIT(2) | 0u)
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#define GPIO_IRQ_RISING (BIT(2) | BIT(1))
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// bits 3-7 pin number, bits 0-3 reg index.
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#define MAKE_GPIO(pin, reg) ((pin)<<3 | (reg))
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typedef enum
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{
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// Not configurable (input only) GPIOs.
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GPIO_1_0 = MAKE_GPIO(0u, 0u), // Bitmask 0x1.
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GPIO_1_1 = MAKE_GPIO(1u, 0u), // Bitmask 0x2.
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GPIO_1_2 = MAKE_GPIO(2u, 0u), // Bitmask 0x4.
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// Configurable GPIOs (direction, IRQ edge, IRQ enable).
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GPIO_2_0 = MAKE_GPIO(0u, 1u), // Bitmask 0x8.
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GPIO_2_1 = MAKE_GPIO(1u, 1u), // Bitmask 0x10.
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// Not configurable (output only) GPIO.
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GPIO_2_2 = MAKE_GPIO(0u, 2u), // Bitmask 0x20. REG_GPIO2_DAT2.
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// Configurable GPIOs (direction, IRQ edge, IRQ enable).
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GPIO_3_0 = MAKE_GPIO(0u, 3u), // Bitmask 0x40.
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GPIO_3_1 = MAKE_GPIO(1u, 3u), // Bitmask 0x80.
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GPIO_3_2 = MAKE_GPIO(2u, 3u), // Bitmask 0x100.
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GPIO_3_3 = MAKE_GPIO(3u, 3u), // Bitmask 0x200.
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GPIO_3_4 = MAKE_GPIO(4u, 3u), // Bitmask 0x400.
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GPIO_3_5 = MAKE_GPIO(5u, 3u), // Bitmask 0x800.
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GPIO_3_6 = MAKE_GPIO(6u, 3u), // Bitmask 0x1000.
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GPIO_3_7 = MAKE_GPIO(7u, 3u), // Bitmask 0x2000.
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GPIO_3_8 = MAKE_GPIO(8u, 3u), // Bitmask 0x4000.
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GPIO_3_9 = MAKE_GPIO(9u, 3u), // Bitmask 0x8000.
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GPIO_3_10 = MAKE_GPIO(10u, 3u), // Bitmask 0x10000.
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GPIO_3_11 = MAKE_GPIO(11u, 3u), // Bitmask 0x20000.
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// Not configurable (output only) GPIO.
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GPIO_3_12 = MAKE_GPIO(0u, 4u), // Bitmask 0x40000. REG_GPIO3_DAT2.
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// -------------------------------------------------------------------------------------------- //
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// Aliases
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GPIO_1_TOUCHSCREEN = GPIO_1_1, // Unset while touchscreen pen down. Unused after CODEC init.
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GPIO_1_SHELL = GPIO_1_2, // 1 when closed.
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GPIO_2_HEADPH_JACK = GPIO_2_0, // Used after CODEC init.
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GPIO_WIFI_IFACE_SEL = GPIO_2_2, // WiFi interface select. 0 = SDIO (Atheros), 1 = DS WiFi (RF Micro Devices, Inc. RF9008/Mitsumi MM3218).
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GPIO_CTR_DEPOP = GPIO_3_0, // Old 3DS only (not XL). Speaker pop suppression circuit.
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GPIO_EXTHID_IRQ = GPIO_3_0, // N3DS/N2DS (XL) only. ZL/ZR pressed and/or C-Stick sample data ready IRQ (falling edge).
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GPIO_IR_NXP_IRQ = GPIO_3_1, // NXP SC16IS750 falling edge IRQ (IR module).
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GPIO_EXTHID_WAKE = GPIO_3_3, // N3DS/N2DS (XL) only. Wakes up the EXTHID chip from sleep if set high?
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GPIO_IR_ROHM_TX_RC = GPIO_3_4, // ROHM RPM841-H11 transmit pin in remote control mode (IR module).
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GPIO_IR_ROHM_RXD = GPIO_3_5, // ROHM RPM841-H11 receive pin (IR module).
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GPIO_3_HEADPH_JACK = GPIO_3_8, // Unused/other function after CODEC init.
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GPIO_CTR_MCU_IRQ = GPIO_3_9, // CTR MCU falling edge IRQ.
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GPIO_ATHEROS_NRST = GPIO_3_12 // Active low reset pin for the Atheros WiFi chipset.
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} Gpio;
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#undef MAKE_GPIO
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/**
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* @brief Configures the specified GPIO.
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*
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* @param[in] gpio The gpio.
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* @param[in] cfg The configuration. See defines above.
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*/
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void GPIO_config(Gpio gpio, u8 cfg);
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/**
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* @brief Reads a GPIO pin.
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*
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* @param[in] gpio The gpio.
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*
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* @return The state. Either 0 or 1.
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*/
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u8 GPIO_read(Gpio gpio);
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/**
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* @brief Writes a GPIO pin.
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*
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* @param[in] gpio The gpio.
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* @param[in] val The value. Must be 0 or 1.
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*/
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void GPIO_write(Gpio gpio, u8 val);
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#ifdef __cplusplus
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} // extern "C"
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#endif |