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124 lines
3.7 KiB
C
124 lines
3.7 KiB
C
#pragma once
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/*
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* This file is part of open_agb_firm
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* Copyright (C) 2021 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <assert.h>
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#include "types.h"
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#include "mem_map.h"
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#define SPICARD_REGS_BASE (IO_MEM_ARM9_ONLY + 0xD800)
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typedef struct
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{
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vu32 cnt; // 0x00
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vu8 cs; // 0x04 32 bit but can be accessed as u8.
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u8 _0x5[3];
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vu32 blklen; // 0x08
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vu32 fifo; // 0x0C
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vu8 fifo_stat; // 0x10 32 bit but can be accessed as u8.
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u8 _0x11[3];
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vu32 autopoll; // 0x14
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vu32 int_mask; // 0x18
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vu32 int_stat; // 0x1C
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} Spic;
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static_assert(offsetof(Spic, int_stat) == 0x1C, "Error: Member int_stat of Spic is not at offset 0x1C!");
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ALWAYS_INLINE Spic* getSpicRegs(void)
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{
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return (Spic*)SPICARD_REGS_BASE;
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}
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// REG_SPIC_CNT
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typedef enum
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{
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SPIC_CLK_512KHz = 0u,
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SPIC_CLK_1MHz = 1u,
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SPIC_CLK_2MHz = 2u,
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SPIC_CLK_4MHz = 3u,
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SPIC_CLK_8MHz = 4u,
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SPIC_CLK_16MHz = 5u,
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// Not a real clock setting. Or with clock
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// to set chip select high after transfer.
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SPIC_CLK_CS_HIGH = 1u<<3
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} SpicClk;
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#define SPIC_BUS_1BIT (0u)
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#define SPIC_BUS_4BIT (1u<<12)
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#define SPIC_DIR_R (0u) // Direction read.
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#define SPIC_DIR_W (1u<<13) // Direction write.
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#define SPIC_EN (1u<<15) // Enable.
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// REG_SPIC_CS
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#define SPIC_CS_HIGH (0u)
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// SPIC_FIFO_STAT
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#define SPIC_FIFO_BUSY (1u)
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// REG_SPIC_AUTOPOLL
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// Shifts.
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#define SPIC_AP_TMOUT_SHIFT (16u) // Auto poll register timeout shift.
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#define SPIC_AP_OFF_SHIFT (24u) // Auto poll register bit offset shift.
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#define SPIC_AP_BIT_SHIFT (30u) // Auto poll register compare bit shift.
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#define SPIC_AP_START (1u<<31) // Auto poll start.
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// REG_SPIC_INT_MASK Bit set = disabled.
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// REG_SPIC_INT_STAT Status and acknowledge.
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#define SPIC_INT_TRAN_END (1u) // Transfer end. Also fires on each auto poll try.
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#define SPIC_INT_AP_MATCH (1u<<1) // Auto poll bit match.
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#define SPIC_INT_AP_TMOUT (1u<<2) // Auto poll timeout.
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// cmd Is the command byte to send.
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// tmout Is the timeout. Must be 0-15. Tries = 31<<(SpicClk + timeout).
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// off Is the bit offset in the response byte. Must be 0-7.
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// cmpBit Is the bit to compare (0 or 1).
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#define MAKE_AP_PARAMS(cmd, tmout, off, cmpBit) ((u32)(cmpBit)<<30 | (u32)(off)<<24 | (u32)(tmout)<<16 | (cmd))
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/**
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* @brief Initializes the SPI bus. Call this only once.
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*/
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void SPICARD_init(void);
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/**
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* @brief Automatically polls a bit of the command response.
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*
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* @param[in] clk The clock frequency to use.
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* @param[in] apParams The parameters. Use the MAKE_AP_PARAMS macro.
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*
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* @return Returns false on timeout and true on bit match.
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*/
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bool SPICARD_autoPollBit(SpicClk clk, u32 apParams);
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/**
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* @brief Writes and/or reads data to/from a SPI device.
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*
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* @param[in] clk The clock frequency to use.
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* @param[in] in Input data pointer for write.
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* @param out Output data pointer for read.
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* @param[in] inSize Input size. Must be <= 0x1FFFFF.
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* @param[in] outSize Output size. Must be <= 0x1FFFFF.
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*/
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void SPICARD_writeRead(SpicClk clk, const u32 *in, u32 *out, u32 inSize, u32 outSize);
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