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https://gitee.com/anod/open_agb_firm.git
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325 lines
15 KiB
C
325 lines
15 KiB
C
#pragma once
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#include <assert.h>
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#include "types.h"
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// For simplicity we will name the accessible 2 controllers 1 and 2.
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// The real controller number is in the comment.
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#ifdef _3DS
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#ifdef ARM9
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#define TOSHSD1_REGS_BASE (0x10006000u) // Controller 1.
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#define TOSHSD2_REGS_BASE (0x10007000u) // Controller 3. Remappable.
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#elif ARM11
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#define TOSHSD1_REGS_BASE (0x10122000u) // Controller 2.
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#define TOSHSD2_REGS_BASE (0x10100000u) // Controller 3. Remappable.
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#endif // #ifdef ARM9
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#define TOSHSD_HCLK (67027964u) // In Hz.
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#elif TWL
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#define TOSHSD1_REGS_BASE (0x04004800u) // Controller 1.
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#define TOSHSD2_REGS_BASE (0x04004A00u) // Controller 2.
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#define TOSHSD_HCLK (33513982u) // In Hz.
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#endif // #ifdef _3DS
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typedef struct
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{
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vu16 sd_cmd; // 0x000
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vu16 sd_portsel; // 0x002
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vu32 sd_arg; // 0x004 SD_ARG0 and SD_ARG1 combined.
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vu16 sd_stop; // 0x008
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vu16 sd_blockcount; // 0x00A
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const vu32 sd_resp[4]; // 0x00C SD_RESP0-7 16 bit reg pairs combined.
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vu32 sd_status; // 0x01C SD_STATUS1 and SD_STATUS2 combined.
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vu32 sd_status_mask; // 0x020 SD_STATUS1_MASK and SD_STATUS2_MASK combined.
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vu16 sd_clk_ctrl; // 0x024
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vu16 sd_blocklen; // 0x026
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vu16 sd_option; // 0x028 Data timeout: 0x2000<<12 / (67027964 / 2) = 1.001206959 sec. Card detect: 0x400<<9 / 67027964 = 0.007821929 sec.
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u8 _0x2a[2];
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const vu32 sd_err_status; // 0x02C SD_ERR_STATUS1 and SD_ERR_STATUS2 combined.
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vu16 sd_fifo; // 0x030
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u8 _0x32[2];
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vu16 sdio_mode; // 0x034
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vu16 sdio_status; // 0x036
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vu16 sdio_status_mask; // 0x038
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u8 _0x3a[0x9e];
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vu16 dma_ext_mode; // 0x0D8
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u8 _0xda[6];
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vu16 soft_rst; // 0x0E0
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const vu16 revision; // 0x0E2 Controller version/revision?
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u8 _0xe4[0xe];
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vu16 unkF2; // 0x0F2 Power related? Default 0. Other values do nothing?
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vu16 unkF4; // 0x0F4 Unknwon. SDIO IRQ related.
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const vu16 ext_wrprot; // 0x0F6 Apparently for eMMC.
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vu16 ext_cdet; // 0x0F8 Card detect status.
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vu16 ext_cdet_dat3; // 0x0FA DAT3 card detect status.
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vu16 ext_cdet_mask; // 0x0FC Card detect mask (IRQ).
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vu16 ext_cdet_dat3_mask; // 0x0FE DAT3 card detect mask (IRQ).
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vu16 sd_fifo32_cnt; // 0x100
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u8 _0x102[2];
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vu16 sd_blocklen32; // 0x104
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u8 _0x106[2];
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vu16 sd_blockcount32; // 0x108
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u8 _0x10a[2];
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vu32 sd_fifo32; // 0x10C Note: This is in the FIFO region on ARM11 (3DS).
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} Toshsd;
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static_assert(offsetof(Toshsd, sd_fifo32) == 0x10C, "Error: Member sd_fifo32 of Toshsd is not at offset 0x10C!");
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ALWAYS_INLINE Toshsd* getToshsdRegs(u8 controller)
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{
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Toshsd *regs;
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switch(controller)
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{
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case 0:
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regs = (Toshsd*)TOSHSD1_REGS_BASE;
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break;
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case 1:
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regs = (Toshsd*)TOSHSD2_REGS_BASE;
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break;
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default:
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regs = (Toshsd*)NULL;
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}
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return regs;
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}
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ALWAYS_INLINE vu32* getToshsdFifo(Toshsd *const regs)
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{
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#if (_3DS && ARM11)
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return (vu32*)((uintptr_t)regs + 0x200000u);
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#else
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return ®s->sd_fifo32;
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#endif // #if (_3DS && ARM11)
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}
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// REG_SD_CMD
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// Bit 0-5 command index.
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#define CMD_ACMD (1u<<6) // Application command.
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#define CMD_RESP_AUTO (0u) // Response type auto. Really?
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#define CMD_RESP_NONE (3u<<8) // Response type none.
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#define CMD_RESP_R1 (4u<<8) // Response type R1 48 bit.
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#define CMD_RESP_R5 (CMD_RESP_R1) // Response type R5 48 bit.
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#define CMD_RESP_R6 (CMD_RESP_R1) // Response type R6 48 bit.
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#define CMD_RESP_R7 (CMD_RESP_R1) // Response type R7 48 bit.
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#define CMD_RESP_R1b (5u<<8) // Response type R1b 48 bit + busy.
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#define CMD_RESP_R5b (CMD_RESP_R1b) // Response type R5b 48 bit + busy.
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#define CMD_RESP_R2 (6u<<8) // Response type R2 136 bit.
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#define CMD_RESP_R3 (7u<<8) // Response type R3 48 bit OCR without CRC.
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#define CMD_RESP_R4 (CMD_RESP_R3) // Response type R4 48 bit OCR without CRC.
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#define CMD_RESP_MASK (CMD_RESP_R3)
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#define CMD_DT (1u<<11) // Data transfer enable.
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#define CMD_DIR_W (0u) // Data transfer direction write.
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#define CMD_DIR_R (1u<<12) // Data transfer direction read.
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#define CMD_MBT (1u<<13) // Multi block transfer (auto STOP_TRANSMISSION).
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#define CMD_SEC_SDIO (1u<<14) // Security/SDIO command.
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// REG_SD_PORTSEL
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#define PORTSEL_P0 (0u) // Controller port 0.
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#define PORTSEL_P1 (1u) // Controller port 1.
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#define PORTSEL_P2 (2u) // Controller port 2.
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#define PORTSEL_P3 (3u) // Controller port 3.
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#define PORTSEL_MASK (PORTSEL_P3)
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// Bit 8-9 number of supported ports?
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#define PORTSEL_UNK10 (1u<<10) // Unknown writable bit 10?
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// REG_SD_STOP
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#define STOP_STOP (1u) // Stop/abort a transfer.
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#define STOP_AUTO_STOP (1u<<8) // Automatically send CMD12 on block transfer end.
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// REG_SD_STATUS1/2 and REG_SD_STATUS1/2_MASK
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// (M) = Maskable bit. 1 = disabled.
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// Unmaskable bits act as status only, don't trigger IRQs and can't be acknowledged.
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#define STATUS_RESP_END (1u) // (M) Response end.
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#define STATUS_DATA_END (1u<<2) // (M) Data transfer end (triggers after last block).
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#define STATUS_REMOVE (1u<<3) // (M) Card got removed.
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#define STATUS_INSERT (1u<<4) // (M) Card got inserted. Set at the same time as DETECT.
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#define STATUS_DETECT (1u<<5) // Card detect status (SD_OPTION detection timer). 1 = inserted.
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#define STATUS_NO_WRPROT (1u<<7) // Write protection slider unlocked (low).
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#define STATUS_DAT3_REMOVE (1u<<8) // (M) Card DAT3 got removed (low).
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#define STATUS_DAT3_INSERT (1u<<9) // (M) Card DAT3 got inserted (high).
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#define STATUS_DAT3_DETECT (1u<<10) // Card DAT3 status. 1 = inserted.
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#define STATUS_ERR_CMD_IDX (1u<<16) // (M) Bad CMD index in response.
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#define STATUS_ERR_CRC (1u<<17) // (M) Bad CRC in response.
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#define STATUS_ERR_STOP_BIT (1u<<18) // (M) Stop bit error. Failed to recognize response frame end?
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#define STATUS_ERR_DATA_TMOUT (1u<<19) // (M) Response data timeout.
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#define STATUS_ERR_RX_OVERF (1u<<20) // (M) Receive FIFO overflow.
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#define STATUS_ERR_TX_UNDERF (1u<<21) // (M) Send FIFO underflow.
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#define STATUS_ERR_CMD_TMOUT (1u<<22) // (M) Response start bit timeout.
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#define STATUS_SD_BUSY (1u<<23) // SD card signals busy if this bit is 0 (DAT0 held low).
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#define STATUS_RX_RDY (1u<<24) // (M) FIFO ready for read.
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#define STATUS_TX_REQ (1u<<25) // (M) FIFO write request.
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// Bit 27 is maskable. Purpose unknown.
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// Bit 29 exists (not maskable). Unknown purpose.
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#define STATUS_CMD_BUSY (1u<<30) // Command register busy.
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#define STATUS_ERR_ILL_ACC (1u<<31) // (M) Illegal access error. TODO: What does that mean?
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#define STATUS_MASK_ALL (STATUS_ERR_ILL_ACC | (1u<<27) | STATUS_TX_REQ | STATUS_RX_RDY | \
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STATUS_ERR_CMD_TMOUT | STATUS_ERR_TX_UNDERF | STATUS_ERR_RX_OVERF | \
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STATUS_ERR_DATA_TMOUT | STATUS_ERR_STOP_BIT | STATUS_ERR_CRC | \
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STATUS_ERR_CMD_IDX | STATUS_DAT3_INSERT | STATUS_DAT3_REMOVE | \
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STATUS_INSERT | STATUS_REMOVE | STATUS_DATA_END | STATUS_RESP_END)
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#define STATUS_MASK_DEFAULT ((1u<<27) | STATUS_TX_REQ | STATUS_RX_RDY | \
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STATUS_DAT3_INSERT | STATUS_DAT3_REMOVE | STATUS_DATA_END)
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#define STATUS_MASK_ERR (STATUS_ERR_ILL_ACC | STATUS_ERR_CMD_TMOUT | STATUS_ERR_TX_UNDERF | \
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STATUS_ERR_RX_OVERF | STATUS_ERR_DATA_TMOUT | STATUS_ERR_STOP_BIT | \
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STATUS_ERR_CRC | STATUS_ERR_CMD_IDX)
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// REG_SD_CLK_CTRL
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#define SD_CLK_DIV_2 (0u) // Clock divider 2.
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#define SD_CLK_DIV_4 (1u) // Clock divider 4.
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#define SD_CLK_DIV_8 (1u<<1) // Clock divider 8.
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#define SD_CLK_DIV_16 (1u<<2) // Clock divider 16.
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#define SD_CLK_DIV_32 (1u<<3) // Clock divider 32.
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#define SD_CLK_DIV_64 (1u<<4) // Clock divider 64.
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#define SD_CLK_DIV_128 (1u<<5) // Clock divider 128.
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#define SD_CLK_DIV_256 (1u<<6) // Clock divider 256.
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#define SD_CLK_DIV_512 (1u<<7) // Clock divider 512.
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#define SD_CLK_EN (1u<<8) // Clock enable.
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#define SD_CLK_AUTO_OFF (1u<<9) // Disables clock on idle.
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// Bit 10 is writable... at least according to gbatek (can't confirm). Purpose unknown.
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// REG_SD_OPTION
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// TODO: Bit 0-3 card detect timer 0x400<<x HCLKs. 0xF timer test.
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// TODO: Bit 4-7 data timeout 0x2000<<x (HCLK / divider). 0xF timeout test.
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#define OPTION_UNK14 (1u<<14) // "no C2 module" What the fuck is a C2 module?
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#define OPTION_BUS_WIDTH4 (0u) // 4 bit bus width.
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#define OPTION_BUS_WIDTH1 (1u<<15) // 1 bit bus width.
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// REG_SD_ERR_STATUS1/2
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// TODO: Are all of these actually supported on this controller?
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#define ERR_RESP_CMD_IDX (1u) // Manual command index error in response.
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#define ERR_RESP_CMD12_IDX (1u<<1) // Auto command index error in response.
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#define ERR_RESP_STOP_BIT (1u<<2) // Manual command response stop bit error.
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#define ERR_RESP_STOP_BIT_CMD12 (1u<<3) // Auto command response stop bit error.
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#define ERR_STOP_BIT_DATA_READ (1u<<4) // Stop bit error in read data.
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#define ERR_STOP_BIT_WR_CRC (1u<<5) // Stop bit error for write CRC status. What the hell does that mean?
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#define ERR_CMD_RESP_CRC (1u<<8) // Manual command response CRC error.
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#define ERR_CMD12_RESP_CRC (1u<<9) // Auto command response CRC error.
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#define ERR_DATA_READ_CRC (1u<<10) // CRC error for read data.
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#define ERR_WR_CRC_STAT (1u<<11) // "CRC error for Write CRC status for a write command". What the hell does that mean?
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// Bit 13 always 1.
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#define ERR_CMD_RESP_TMOUT (1u<<16) // Manual command response timeout.
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#define ERR_CMD12_RESP_TMOUT (1u<<17) // Auto command response timeout.
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// TODO: Add the correct remaining ones.
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// REG_SDIO_MODE
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// REG_SDIO_STATUS and REG_SDIO_STATUS_MASK
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// REG_DMA_EXT_MODE
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#define DMA_EXT_CPU_MODE (0u) // Disables DMA requests. Actually also turns off the 32 bit FIFO.
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#define DMA_EXT_DMA_MODE (1u<<1) // Enables DMA requests.
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#define DMA_EXT_UNK5 (1u<<5) // "Buffer status mode"?
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// REG_SOFT_RST
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#define SOFT_RST_RST (0u) // Reset.
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#define SOFT_RST_NORST (1u) // No reset.
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// REG_EXT_WRPROT
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// 1 = Write protected unlike SD_STATUS.
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#define EXT_WRPROT_PORT1 (1u)
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#define EXT_WRPROT_PORT2 (1u<<1)
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#define EXT_WRPROT_PORT3 (1u<<2)
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// REG_EXT_CDET and REG_EXT_CDET_MASK
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// (M) = Maskable bit. 1 = disabled (no IRQ).
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#define EXT_CDET_P1_REMOVE (1u) // (M) Port 1 card got removed.
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#define EXT_CDET_P1_INSERT (1u<<1) // (M) Port 1 card got inserted. TODO: With detection timer?
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#define EXT_CDET_P1_DETECT (1u<<2) // Port 1 card detect status. 1 = inserted. TODO: With detection timer?
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#define EXT_CDET_P2_REMOVE (1u<<3) // (M) Port 2 card got removed.
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#define EXT_CDET_P2_INSERT (1u<<4) // (M) Port 2 card got inserted. TODO: With detection timer?
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#define EXT_CDET_P2_DETECT (1u<<5) // Port 2 card detect status. 1 = inserted. TODO: With detection timer?
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#define EXT_CDET_P3_REMOVE (1u<<6) // (M) Port 3 card got removed.
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#define EXT_CDET_P3_INSERT (1u<<7) // (M) Port 3 card got inserted. TODO: With detection timer?
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#define EXT_CDET_P3_DETECT (1u<<8) // Port 3 card detect status. 1 = inserted. TODO: With detection timer?
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#define EXT_CDET_MASK_ALL (EXT_CDET_P3_INSERT | EXT_CDET_P3_REMOVE | EXT_CDET_P2_INSERT | \
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EXT_CDET_P2_REMOVE | EXT_CDET_P1_INSERT | EXT_CDET_P1_REMOVE)
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// REG_EXT_CDET_DAT3 and REG_EXT_CDET_DAT3_MASK
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// (M) = Maskable bit. 1 = disabled (no IRQ).
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#define EXT_CDET_DAT3_P1_REMOVE (1u) // (M) Port 1 card DAT3 got removed (low).
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#define EXT_CDET_DAT3_P1_INSERT (1u<<1) // (M) Port 1 card DAT3 got inserted (high).
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#define EXT_CDET_DAT3_P1_DETECT (1u<<2) // Port 1 card DAT3 status. 1 = inserted.
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#define EXT_CDET_DAT3_P2_REMOVE (1u<<3) // (M) Port 2 card DAT3 got removed (low).
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#define EXT_CDET_DAT3_P2_INSERT (1u<<4) // (M) Port 2 card DAT3 got inserted (high).
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#define EXT_CDET_DAT3_P2_DETECT (1u<<5) // Port 2 card DAT3 status. 1 = inserted.
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#define EXT_CDET_DAT3_P3_REMOVE (1u<<6) // (M) Port 3 card DAT3 got removed (low).
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#define EXT_CDET_DAT3_P3_INSERT (1u<<7) // (M) Port 3 card DAT3 got inserted (high).
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#define EXT_CDET_DAT3_P3_DETECT (1u<<8) // Port 3 card DAT3 status. 1 = inserted.
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#define EXT_CDET_DAT3_MASK_ALL (EXT_CDET_DAT3_P3_INSERT | EXT_CDET_DAT3_P3_REMOVE | EXT_CDET_DAT3_P2_INSERT | \
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EXT_CDET_DAT3_P2_REMOVE | EXT_CDET_DAT3_P1_INSERT | EXT_CDET_DAT3_P1_REMOVE)
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// REG_SD_FIFO32_CNT
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#define FIFO32_UNK1 (1u) // Unknown bit.
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#define FIFO32_EN (1u<<1) // Enables the 32 bit FIFO.
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#define FIFO32_FULL (1u<<8) // FIFO is full.
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#define FIFO32_NOT_EMPTY (1u<<9) // FIFO is not empty. Inverted bit. 0 means empty.
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#define FIFO32_CLEAR (1u<<10) // Clears the FIFO.
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#define FIFO32_FULL_IE (1u<<11) // FIFO full IRQ enable.
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#define FIFO32_NOT_EMPTY_IE (1u<<12) // FIFO not empty IRQ enable.
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typedef struct
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{
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u8 portNum;
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u16 sd_clk_ctrl;
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u16 sd_blocklen; // Also sd_blocklen32.
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u16 sd_option;
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u32 *buf;
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u16 blocks;
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u32 resp[4]; // Little endian, MSB first.
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} ToshsdPort;
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// See status defines in regs/toshsd.h for details.
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#define TSD_ERR_CMD_IDX (1u<<16)
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#define TSD_ERR_CRC (1u<<17)
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#define TSD_ERR_STOP_BIT (1u<<18)
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#define TSD_ERR_DATA_TMOUT (1u<<19)
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#define TSD_ERR_RX_OVERF (1u<<20)
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#define TSD_ERR_TX_UNDERF (1u<<21)
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#define TSD_ERR_CMD_TMOUT (1u<<22)
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#define TSD_ERR_ILL_ACC (1u<<31)
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void TOSHSD_init(void);
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void TOSHSD_deinit(void);
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void TOSHSD_initPort(ToshsdPort *const port, u8 portNum);
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bool TOSHSD_cardDetected(void);
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bool TOSHSD_cardSliderUnlocked(void);
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void TOSHSD_setClock(ToshsdPort *const port, u16 clk);
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u32 TOSHSD_sendCommand(ToshsdPort *const port, u16 cmd, u32 arg);
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ALWAYS_INLINE void TOSHSD_setBlockLen(ToshsdPort *const port, u16 blockLen)
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{
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if(blockLen > 512) blockLen = 512;
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if(blockLen < 16) blockLen = 0;
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if((blockLen % 16) != 0) blockLen = 0;
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port->sd_blocklen = blockLen;
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}
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ALWAYS_INLINE void TOSHSD_setBusWidth(ToshsdPort *const port, u8 width)
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{
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// TODO: Make this more readable.
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if(width == 4) port->sd_option = 1u<<14 | 0xE9;
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else port->sd_option = 1u<<15 | 1u<<14 | 0xE9u;
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}
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ALWAYS_INLINE void TOSHSD_setBuffer(ToshsdPort *const port, u32 *buf, u16 blocks)
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{
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port->buf = buf;
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port->blocks = blocks;
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}
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#ifdef ARM11
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void TOSHSD_dbgPrint(ToshsdPort *const port);
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#endif
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