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78da297199
gfx: 常量大改名、函数大改名，增加了双缓冲的一些驱动函数 其他：基本是ARM9/ARM11宏修改和BIT取值修改，bool从c风格转成c++强类型风格等。sha.c使用了memory.h进行的改动(copy32)
236 lines
9.1 KiB
C
236 lines
9.1 KiB
C
#pragma once
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/*
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* This file is part of libn3ds
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* Copyright (C) 2024 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "types.h"
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#include "mem_map.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//#define USE_NEW_CDMA (1)
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#ifdef __ARM11__
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#ifdef USE_NEW_CDMA
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#define DMA330_REGS_BASE (IO_AXI_BASE + 0x6000)
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#else
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#define DMA330_REGS_BASE (IO_AXI_BASE + 0x0000)
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#endif // ifdef USE_NEW_CDMA
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#elif __ARM9__
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#define DMA330_REGS_BASE (IO_AHB_BASE + 0xC000)
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#endif // ifdef __ARM11__
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typedef struct
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{
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const vu32 dsr; // 0x000 DMA Manager Status Register.
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const vu32 dpc; // 0x004 DMA Program Counter Register (manager).
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u8 _0x8[0x18];
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vu32 inten; // 0x020 Interrupt Enable Register.
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const vu32 int_event_ris; // 0x024 Event-Interrupt Raw Status Register.
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const vu32 intmis; // 0x028 Interrupt Status Register.
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vu32 intclr; // 0x02C Interrupt Clear Register (write-only).
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const vu32 fsrd; // 0x030 Fault Status DMA Manager Register.
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const vu32 fsrc; // 0x034 Fault Status DMA Channel Register.
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const vu32 ftrd; // 0x038 Fault Type DMA Manager Register.
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u8 _0x3c[4];
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const vu32 ftr[8]; // 0x040 Fault Type DMA Channel Registers.
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u8 _0x60[0xa0];
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struct // 0x100
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{
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const vu32 csr; // 0x0 Channel Status Register.
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const vu32 cpc; // 0x4 Channel Program Counter Register.
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} chStat[8];
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u8 _0x140[0x2c0];
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struct // 0x400
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{
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const vu32 sar; // 0x00 Source Address Register.
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const vu32 dar; // 0x04 Destination Address Register.
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const vu32 ccr; // 0x08 Channel Control Register.
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const vu32 lc0; // 0x0C Loop Counter 0 Register.
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const vu32 lc1; // 0x10 Loop Counter 1 Register.
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u8 chCtrl_0x14[0xc];
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} chCtrl[8];
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u8 _0x500[0x800];
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const vu32 dbgstatus; // 0xD00 Debug Status Register.
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vu32 dbgcmd; // 0xD04 Debug Command Register (write-only).
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vu32 dbginst0; // 0xD08 Debug Instruction-0 Register (write-only).
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vu32 dbginst1; // 0xD0C Debug Instruction-1 Register (write-only).
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u8 _0xd10[0xf0];
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const vu32 cr0; // 0xE00 Configuration Register 0.
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const vu32 cr1; // 0xE04 Configuration Register 1.
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const vu32 cr2; // 0xE08 Configuration Register 2.
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const vu32 cr3; // 0xE0C Configuration Register 3.
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const vu32 cr4; // 0xE10 Configuration Register 4.
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const vu32 crd; // 0xE14 DMA Configuration Register.
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u8 _0xe18[0x68];
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vu32 wd; // 0xE80 Watchdog Register (r1p0 only).
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u8 _0xe84[0x15c];
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const vu32 periph_id_0; // Peripheral Identification Register 0.
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const vu32 periph_id_1; // Peripheral Identification Register 1.
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const vu32 periph_id_2; // Peripheral Identification Register 2.
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const vu32 periph_id_3; // Peripheral Identification Register 3.
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const vu32 pcell_id_0; // Component Identification Register 0.
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const vu32 pcell_id_1; // Component Identification Register 1.
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const vu32 pcell_id_2; // Component Identification Register 2.
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const vu32 pcell_id_3; // Component Identification Register 3.
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} Dma330;
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static_assert(offsetof(Dma330, pcell_id_3) == 0xFFC, "Error: Member pcell_id_3 of Dma330 is not at offset 0xFFC!");
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ALWAYS_INLINE Dma330* getDma330Regs(void)
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{
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return (Dma330*)DMA330_REGS_BASE;
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}
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// REG_DMA330_DSR
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#define DSR_WAKE_EVNT_SHIFT (4u)
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#define DSR_WAKE_EVNT_MASK (0x1Fu<<DSR_WAKEUP_EVNT_SHIFT)
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#define DSR_DNS BIT(9) // DMA Manager is non-secure.
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enum
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{
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DSR_STAT_STOPPED = 0u,
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DSR_STAT_EXECUTING = 1u,
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DSR_STAT_CACHE_MISS = 2u,
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DSR_STAT_UPDATING_PC = 3u, // Updating program counter.
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DSR_STAT_WFE = 4u, // Waiting for event.
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DSR_STAT_FAULTING = 15u,
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DSR_STAT_MASK = DSR_STAT_FAULTING
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};
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// REG_DMA330_INTEN
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#define INTEN_SEL_IRQ(n) BIT(n) // Select IRQ instead of event.
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// REG_DMA330_INT_EVENT_RIS
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#define INT_EVENT_RIS_ACTIVE(n) BIT(n) // Interrupt or event N is active.
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// REG_DMA330_INTMIS
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#define INTMIS_IRQ_ACTIVE(n) BIT(n) // Interrupt N is active.
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// REG_DMA330_INTCLR
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#define INTCLR_IRQ_CLR(n) BIT(n) // Clear interrupt N.
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// REG_DMA330_FSRD
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#define FSRD_FAULTING BIT(0) // DMA manager is in faulting state.
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// REG_DMA330_FSRC
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#define FSRC_FAULTING(n) BIT(n) // DMA channel is in faulting or faulting completing state.
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// REG_DMA330_FTRD
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#define FTRD_UNDEF_INSTR BIT(0)
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#define FTRD_OPERAND_INVALID BIT(1)
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#define FTRD_DMAGO_ERR BIT(4) // Starting a secure channel from a non-secure state.
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#define FTRD_MGR_EVNT_ERR BIT(5) // Waiting for or creating secure events/interrupts in no-secure state.
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#define FTRD_INSTR_FETCH_ERR BIT(16)
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#define FTRD_DBG_INSTR BIT(30) // The erroneous instruction came from the debug interface.
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// REG_DMA330_FTR0-7
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#define FTR_UNDEF_INSTR BIT(0)
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#define FTR_OPERAND_INVALID BIT(1)
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#define FTR_CH_EVNT_ERR BIT(5) // Waiting for or creating secure events/interrupts in no-secure state.
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#define FTR_CH_PERIPH_ERR BIT(6) // Accessing secure periphals in non-secure state (DMAWFP, DMALDP, DMASTP, DMAFLUSHP).
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#define FTR_CH_RDWR_ERR BIT(7) // Secure read or write in non-secure state.
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#define FTR_CH_MFIFO_ERR BIT(12) // MFIFO too small to hold or store the data (DMALD, DMAST).
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#define FTR_CH_ST_DATA_UNAVAIL BIT(13) // Not enough data in the MFIFO for DMAST to complete.
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#define FTR_INSTR_FETCH_ERR BIT(16)
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#define FTR_DATA_WRITE_ERR BIT(17)
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#define FTR_DATA_READ_ERR BIT(18)
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#define FTR_DBG_INSTR BIT(30) // The erroneous instruction came from the debug interface.
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#define FTR_LOCKUP_ERR BIT(31) // Channel locked up because of resource starvation.
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// REG_DMA330_CSR0-7
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#define CSR_WAKE_EVNT_SHIFT (4u)
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#define CSR_WAKE_EVNT_MASK (0x1Fu<<CSR_WAKEUP_EVNT_SHIFT)
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#define CSR_DMAWFP_B_NS BIT(14) // DMAWFP executed with burst operand set.
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#define CSR_DMAWFP_PERIPH BIT(15) // DMAWFP executed with periph operand set.
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#define CSR_CNS BIT(21) // DMA channel is non-secure.
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enum
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{
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CSR_STAT_STOPPED = 0u,
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CSR_STAT_EXECUTING = 1u,
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CSR_STAT_CACHE_MISS = 2u,
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CSR_STAT_UPDATING_PC = 3u, // Updating program counter.
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CSR_STAT_WFE = 4u, // Waiting for event.
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CSR_STAT_AT_BARRIER = 5u,
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CSR_STAT_WFP = 7u, // Waiting for periphal.
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CSR_STAT_KILLING = 8u,
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CSR_STAT_COMPLETING = 9u,
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CSR_STAT_FAULTING_COMPLETING = 14u,
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CSR_STAT_FAULTING = 15u,
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CSR_STAT_MASK = CSR_STAT_FAULTING
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};
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// REG_DMA330_CCR0-7
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#define CCR_SRC_INC BIT(0)
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#define CCR_SRC_BURST_SIZE_SHIFT (1u)
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#define CCR_SRC_BURST_SIZE_MASK (0x7u<<CCR_SRC_BURST_SIZE_SHIFT)
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#define CCR_SRC_BURST_LEN_SHIFT (4u)
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#define CCR_SRC_BURST_LEN_MASK (0xFu<<CCR_SRC_BURST_LEN_SHIFT)
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#define CCR_SRC_PROT_CTRL_SHIFT (8u)
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#define CCR_SRC_PROT_CTRL_MASK (0x7u<<CCR_SRC_PROT_CTRL_SHIFT)
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#define CCR_SRC_CACHE_CTRL_SHIFT (11u)
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#define CCR_SRC_CACHE_CTRL_MASK (0x7u<<CCR_SRC_CACHE_CTRL_SHIFT)
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#define CCR_DST_INC BIT(14)
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#define CCR_DST_BURST_SIZE_SHIFT (15u)
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#define CCR_DST_BURST_SIZE_MASK (0x7u<<CCR_DST_BURST_SIZE_SHIFT)
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#define CCR_DST_BURST_LEN_SHIFT (18u)
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#define CCR_DST_BURST_LEN_MASK (0xFu<<CCR_DST_BURST_LEN_SHIFT)
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#define CCR_DST_PROT_CTRL_SHIFT (22u)
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#define CCR_DST_PROT_CTRL_MASK (0x7u<<CCR_DST_PROT_CTRL_SHIFT)
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#define CCR_DST_CACHE_CTRL_SHIFT (25u)
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#define CCR_DST_CACHE_CTRL_MASK (0x7u<<CCR_DST_CACHE_CTRL_SHIFT)
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#define CCR_END_SWP_SIZE_SHIFT (28u) // Endian swap size.
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#define CCR_END_SWP_SIZE_MASK (0x7u<<CCR_END_SWP_SIZE_SHIFT)
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// REG_DMA330_DBGSTATUS
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#define DBGSTATUS_BUSY BIT(0)
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// REG_DMA330_DBGCMD
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#define DBGCMD_EXECUTE (0u)
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// REG_DMA330_DBGINST0
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#define DBGINST0_THR_MGR (0u) // Select DMA manager thread.
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#define DBGINST0_THR_CH BIT(0) // Select DMA channel thread (also needs a channel number).
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#define DBGINST0(b10, ch, t) ((b10)<<16 | (ch)<<8 | (t)) // b10 = byte 1 and 0, ch = channel num, t = thread.
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// DBGINST1 stores the remaining 4 instruction bytes.
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void DMA330_init(void); // For libn3ds internal usage only.
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u8 DMA330_run(u8 ch, const u8 *const prog);
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u8 DMA330_status(u8 ch);
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void DMA330_ackIrq(u8 eventIrq);
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void DMA330_sev(u8 event);
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void DMA330_kill(u8 ch);
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#ifdef __ARM11__
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//void DMA330_dbgPrint(void);
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#endif // ifdef __ARM11__
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#ifdef __cplusplus
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} // extern "C"
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#endif |