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250 lines
8.0 KiB
C
250 lines
8.0 KiB
C
/*
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* This file is part of libn3ds
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* Copyright (C) 2024 profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include "types.h"
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#include "arm11/drivers/lgycap.h"
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#include "arm11/drivers/interrupt.h"
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#include "drivers/cache.h"
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#include "drivers/corelink_dma-330.h"
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#include "arm11/drivers/gx.h"
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#include "kevent.h"
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static KHandle g_frameReadyEvents[2] = {0, 0};
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// DMA330 docs don't tell you the recommended alignment so we assume it's bus width.
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alignas(8) static u8 g_lgyCapDmaProg[44] =
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{
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// All transfer settings for A1BGR5 at 360x240 to a 512x512 texture.
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0xBC, 0x01, 0xF6, 0xC2, 0xBD, 0x00, // MOV CCR, SB16 SS64 SAF SP2 DB16 DS64 DAI DP2
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0xBC, 0x00, 0x00, 0x10, 0x31, 0x10, // MOV SAR, 0x10311000
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0x35, 0x70, // FLUSHP 14
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0x20, 0x01, // LP 2
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0xBC, 0x02, 0x00, 0x00, 0x20, 0x18, // MOV DAR, 0x18200000
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// LPFE
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0x31, 0x70, // WFP 14, periph
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0x22, 0x2B, // LP 44
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0x04, // LD
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0x08, // ST
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0x3C, 0x02, // LPEND
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0x27, 0x70, // LDPB 14
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0x08, // ST
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0x56, 0x80, 0x09, // ADDH DAR, 0x980
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0x28, 0x0E, // LPEND
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0x13, // WMB
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0x34, 0x08, // SEV 1
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0x38, 0x1B, // LPEND ; Modified to jump to "LP 2" so the loop can never exit.
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0x00 // END
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};
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static void dmaIrqHandler(const u32 intSource)
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{
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// Acknowledge the IRQ from CDMA.
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static_assert(IRQ_CDMA_EVENT0 + 1 == IRQ_CDMA_EVENT1);
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const u32 dev = intSource - IRQ_CDMA_EVENT0;
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DMA330_ackIrq(dev);
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// We can't match the GBA refreshrate exactly so keep the LCDs around 90%
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// ahead of the GBA output which gives us a time window of around 1.6 ms to
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// render the frame and hopefully reduces output lag as much as possible.
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// Note: Some capture cards don't like the LCDs running out of sync
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// so we have to adjust both v_total.
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GxRegs *const gx = getGxRegs();
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u32 vtotal;
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if(gx->pdc0.v_count > 414 - 41) vtotal = 415; // Slower than GBA.
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else vtotal = 414; // Faster than GBA.
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gx->pdc0.v_total = vtotal;
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gx->pdc1.v_total = vtotal;
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// Wide mode:
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/*u32 vtotal;
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if(pdc0->v_count > 828 - 82) vtotal = 830; // Slower than GBA.
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else vtotal = 829; // Faster than GBA.
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pdc0->v_total = vtotal;*/
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signalEvent(g_frameReadyEvents[dev], false);
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}
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// This is a temporary solution and will be replaced by a DMA JIT eventually.
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static bool patchDmaProg(const u16 width, const u32 pixelSize)
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{
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u8 *const prog = g_lgyCapDmaProg;
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// Test if we can divide the size of 8 lines by DMA burst size.
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const u32 bytesPer8Lines = width * pixelSize * 8;
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u32 transfers = 16;
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if(bytesPer8Lines % (16 * 8) == 0)
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{
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// Patch DMA prog to do 16 transfers of 8 bytes each.
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prog[2] = 0xF6; // SB16.
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prog[4] = 0xBD; // DB16.
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}
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else if(bytesPer8Lines % (15 * 8) == 0)
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{
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// Patch DMA prog to do 15 transfers of 8 bytes each.
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transfers = 15;
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prog[2] = 0xE6; // SB15.
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prog[4] = 0xB9; // DB15.
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}
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else return false;
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// Adjust inner loop count. The last transfer is not part of the loop.
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prog[25] = (bytesPer8Lines / (transfers * 8)) - 2;
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// Skip padding pixels at the right side of the sub texture.
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const u16 gapSize = (512u - width) * pixelSize * 8;
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memcpy(&prog[34], &gapSize, 2);
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// Make sure the DMA controller can see the code.
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flushDCacheRange(prog, sizeof(g_lgyCapDmaProg));
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return true;
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}
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/*
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* Scaler matrix limitations:
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* First pattern bit must be 1 and last 0 (for V-scale) or it loses sync with the DS/GBA input.
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* Vertical scaling is fucked with identity matrix.
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*
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* Matrix ranges:
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* in[-3] -1024-1023 (0xFC00-0x03FF)
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* in[-2] -4096-4095 (0xF000-0x0FFF)
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* in[-1] -32768-32767 (0x8000-0x7FFF)
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* in[0] -32768-32767 (0x8000-0x7FFF)
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* in[1] -4096-4095 (0xF000-0x0FFF)
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* in[2] -1024-1023 (0xFC00-0x03FF)
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*
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* Note: At scanline start the in FIFO is all filled with the first pixel.
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* Note: The first column only allows 1 non-zero entry.
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* Note: Bits 0-3 of each entry are ignored by the hardware.
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* Note: 16384 (0x4000) is the maximum brightness of a pixel.
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* The sum of all entries in a column should be 16384 or clipping will occur.
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* Note: The window of (the 6) input pixels is post-increment.
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* When the matching pattern bit is 0 it does not move forward.
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*/
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static void setScalerMatrix(LgyCapScaler *const scaler, const u32 len, const u32 patt, const s16 *in)
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{
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scaler->len = len - 1;
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scaler->patt = patt;
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vu32 *out = &scaler->matrix[0][0];
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unsigned i = 0;
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do
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{
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*out++ = *in++;
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} while(++i < 6 * 8);
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}
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static inline u32 getPixelSize(const u32 lgycap_cnt)
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{
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const u32 fmt = (lgycap_cnt>>8) & 3u;
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return (fmt == (LGYCAP_FMT_BGR565>>8) ? 2 : 4 - fmt);
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}
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KHandle LGYCAP_init(const LgyCapDev dev, const LgyCapCfg *const cfg)
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{
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if(!patchDmaProg(cfg->w, getPixelSize(cfg->cnt))) return 0;
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if(DMA330_run(dev, g_lgyCapDmaProg)) return 0;
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// Create KEvent for frame ready signal.
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KHandle frameReadyEvent = createEvent(false);
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g_frameReadyEvents[dev] = frameReadyEvent;
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LgyCap *const lgyCap = getLgyCapRegs(dev);
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lgyCap->dim = LGYCAP_DIM(cfg->w, cfg->h);
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lgyCap->irq = cfg->irq;
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lgyCap->stat = LGYCAP_IRQ_MASK; // Acknowledge all IRQs.
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lgyCap->alpha = 0xFF;
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// Hardware bug:
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// The dither pattern *must* be initialized.
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// The dither enable bits in REG_LGYCAP_CNT are broken and do nothing.
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// 0xCCCC will force the hardware to apply no dithering.
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lgyCap->dither_patt0 = 0xCCCC;
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lgyCap->dither_patt1 = 0xCCCC;
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lgyCap->dither_patt2 = 0xCCCC;
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lgyCap->dither_patt3 = 0xCCCC;
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// Setup hardware scaling.
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setScalerMatrix(&lgyCap->vscaler, cfg->vLen, cfg->vPatt, cfg->vMatrix);
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setScalerMatrix(&lgyCap->hscaler, cfg->hLen, cfg->hPatt, cfg->hMatrix);
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// Color accuracy notes:
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// In GBA mode with BGR8 output format color channels are converted with "val<<3".
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// The green channel is special and uses "(val<<3) + 2" instead.
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// DS mode is untested but likely "val<<2" (green offset unknown).
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// A1BGR5 is ideal for GBA mode since we get the 5 bits per channel we want directly.
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lgyCap->cnt = LGYCAP_DMA_EN | cfg->cnt | LGYCAP_EN;
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IRQ_registerIsr(IRQ_CDMA_EVENT0 + dev, 13, 0, dmaIrqHandler);
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return frameReadyEvent;
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}
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void LGYCAP_deinit(const LgyCapDev dev)
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{
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// Disable LgyCap engine.
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LgyCap *const lgyCap = getLgyCapRegs(dev);
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lgyCap->cnt = 0;
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// Acknowledge all IRQs.
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lgyCap->stat = LGYCAP_IRQ_MASK;
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// Kill the DMA channel and flush the FIFO.
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DMA330_kill(dev);
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lgyCap->flush = 0;
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// Unregister interrupt service routine.
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IRQ_unregisterIsr(IRQ_CDMA_EVENT0 + dev);
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// Delete event if one was created previously.
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if(g_frameReadyEvents[dev] != 0)
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{
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deleteEvent(g_frameReadyEvents[dev]);
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}
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g_frameReadyEvents[dev] = 0;
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}
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void LGYCAP_stop(const LgyCapDev dev)
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{
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// Disable LgyCap engine.
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LgyCap *const lgyCap = getLgyCapRegs(dev);
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lgyCap->cnt &= ~LGYCAP_EN;
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// Acknowledge all IRQs.
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lgyCap->stat = LGYCAP_IRQ_MASK;
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// Kill the DMA channel and flush the FIFO.
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DMA330_kill(dev);
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lgyCap->flush = 0;
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// Clear event to prevent issues since we just disabled LgyCap.
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if(g_frameReadyEvents[dev] != 0)
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{
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clearEvent(g_frameReadyEvents[dev]);
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}
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}
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void LGYCAP_start(const LgyCapDev dev)
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{
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// Restart DMA followed by LgyCap.
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if(DMA330_run(dev, g_lgyCapDmaProg)) return;
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getLgyCapRegs(dev)->cnt |= LGYCAP_EN;
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} |