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https://gitee.com/anod/open_agb_firm.git
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346 lines
9.9 KiB
ArmAsm
346 lines
9.9 KiB
ArmAsm
/*
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* This file is part of open_agb_firm
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* Copyright (C) 2021 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "arm.h"
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#include "mem_map.h"
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.cpu arm946e-s
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.fpu softvfp
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.macro BEGIN_ASM_FUNC name, type=arm, linkage=global
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.if \type == thumb
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.align 1
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.thumb
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.else
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.align 2
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.arm
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.endif
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.\linkage \name
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.type \name, %function
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.func \name
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.cfi_sections .debug_frame
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.cfi_startproc
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\name:
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.endm
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.macro END_ASM_FUNC
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.cfi_endproc
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.endfunc
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.endm
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.section .crt0, "ax", %progbits
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BEGIN_ASM_FUNC _start
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@ 如果argc > 0，则保存argv的字符串到0x20001000，也就是RAM_FIRM_BOOT_ADDR
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cmp r0, #0
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beq _start_firm
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mov r0, #0x20000000
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add r0, #0x1000
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ldr r1, [r1] @ r1 = r1[0]
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_strcpy_firm:
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ldrb r2, [r1], #1 @ r2 = *r1
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strb r2, [r0], #1 @ *r0 = r2
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cmp r2, #0
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bne _strcpy_firm
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_start_firm:
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msr cpsr_cxsf, #PSR_INT_OFF | PSR_SVC_MODE
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@ Control register:
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@ [19] ITCM load mode : disabled
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@ [18] ITCM : disabled
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@ [17] DTCM load mode : disabled
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@ [16] DTCM : disabled
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@ [15] Disable loading TBIT : disabled
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@ [14] Round-robin replacement: disabled
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@ [13] Vector select : 0xFFFF0000
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@ [12] I-Cache : disabled
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@ [7] Endianess : little
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@ [2] D-Cache : disabled
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@ [0] MPU : disabled
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ldrh r3, =0x2078
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mov r4, #0
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mcr p15, 0, r3, c1, c0, 0 @ Write control register
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mcr p15, 0, r4, c7, c5, 0 @ Invalidate I-Cache
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mcr p15, 0, r4, c7, c6, 0 @ Invalidate D-Cache
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mcr p15, 0, r4, c7, c10, 4 @ Drain write buffer
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bl setupExceptionVectors @ Setup the vectors in ARM9 mem bootrom vectors jump to
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bl setupTcms @ Setup and enable DTCM and ITCM
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mov sp, #0 @ unused SVC mode sp
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msr cpsr_cxsf, #PSR_INT_OFF | PSR_IRQ_MODE
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ldr sp, =A9_IRQ_STACK_END
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ldr r0, =A9_EXC_STACK_END
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msr cpsr_cxsf, #PSR_INT_OFF | PSR_ABORT_MODE
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mov sp, r0
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msr cpsr_cxsf, #PSR_INT_OFF | PSR_UNDEF_MODE
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mov sp, r0
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msr cpsr_cxsf, #PSR_INT_OFF | PSR_SYS_MODE
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ldr sp, =A9_STACK_END
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bl setupMpu
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@ Clear bss section
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ldr r0, =__bss_start__
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ldr r1, =__bss_end__
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sub r2, r1, r0
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mov r1, #0
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bl iomemset
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@ Setup newlib heap
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ldr r0, =IO_MEM_ARM9_ONLY @ CFG9 regs
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ldr r1, [r0, #0xFFC] @ REG_CFG9_SOCINFO
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tst r1, #2 @ Test for LGR1 bit (New 3DS prototype).
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movne r2, #1
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strne r2, [r0, #0x200] @ REG_CFG9_EXTMEMCNT9
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ldr r0, =A9_HEAP_END
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addne r0, #A9_RAM_N3DS_EXT_SIZE
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ldr r1, =fake_heap_end
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str r0, [r1]
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blx __libc_init_array @ Initialize ctors and dtors
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blx __systemInit
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mov r0, #0 @ argc
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adr r1, _dummyArgv @ argv
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blx main
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blx __systemDeinit
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_start_lp:
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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b _start_lp
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.pool
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_dummyArgv:
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.4byte 0
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END_ASM_FUNC
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#define MAKE_BRANCH(src, dst) (0xEA000000 | (((((dst) - (src)) >> 2) - 2) & 0xFFFFFF))
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BEGIN_ASM_FUNC setupExceptionVectors
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adr r0, _vectorStubs
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ldr r1, =A9_VECTORS_START
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ldmia r0!, {r2-r9}
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stmia r1!, {r2-r9}
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ldm r0, {r2-r5}
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stm r1, {r2-r5}
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bx lr
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.pool
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_vectorStubs:
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ldr pc, irqHandlerPtr
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irqHandlerPtr: .4byte irqHandler
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udf #2
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fiqHandlerPtr: .4byte (A9_VECTORS_START + 0x08)
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udf #3
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svcHandlerPtr: .4byte (A9_VECTORS_START + 0x10)
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ldr pc, undefInstrHandlerPtr
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undefInstrHandlerPtr: .4byte undefInstrHandler
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ldr pc, prefetchAbortHandlerPtr
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prefetchAbortHandlerPtr: .4byte prefetchAbortHandler
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ldr pc, dataAbortHandlerPtr
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dataAbortHandlerPtr: .4byte dataAbortHandler
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END_ASM_FUNC
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BEGIN_ASM_FUNC setupTcms
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ldr r1, =(ITCM_BASE | 0x24) @ Base = 0x00000000, size = 128 MiB (32 KiB mirrored)
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ldr r0, =(DTCM_BASE | 0x0A) @ Base = 0xFFF00000, size = 16 KiB
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mcr p15, 0, r0, c9, c1, 0 @ Write DTCM region reg
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mcr p15, 0, r1, c9, c1, 1 @ Write ITCM region reg
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mrc p15, 0, r0, c1, c0, 0 @ Read control register
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orr r0, r0, #0x50000 @ Enable DTCM and ITCM
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mcr p15, 0, r0, c1, c0, 0 @ Write control register
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bx lr
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.pool
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END_ASM_FUNC
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#define REGION_4KiB (0b01011)
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#define REGION_8KiB (0b01100)
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#define REGION_16KiB (0b01101)
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#define REGION_32KiB (0b01110)
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#define REGION_64KiB (0b01111)
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#define REGION_128KiB (0b10000)
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#define REGION_256KiB (0b10001)
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#define REGION_512KiB (0b10010)
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#define REGION_1MiB (0b10011)
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#define REGION_2MiB (0b10100)
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#define REGION_4MiB (0b10101)
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#define REGION_8MiB (0b10110)
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#define REGION_16MiB (0b10111)
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#define REGION_32MiB (0b11000)
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#define REGION_64MiB (0b11001)
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#define REGION_128MiB (0b11010)
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#define REGION_256MiB (0b11011)
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#define REGION_512MiB (0b11100)
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#define REGION_1GiB (0b11101)
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#define REGION_2GiB (0b11110)
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#define REGION_4GiB (0b11111)
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#define MAKE_REGION(adr, size) ((adr) | ((size)<<1) | 1)
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#define PER_NA (0)
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#define PER_PRIV_RW_USR_NA (0b0001)
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#define PER_PRIV_RW_USR_RO (0b0010)
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#define PER_PRIV_RW_USR_RW (0b0011)
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#define PER_PRIV_RO_USR_NA (0b0101)
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#define PER_PRIV_RO_USR_RO (0b0110)
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#define MAKE_PERMISSIONS(r0, r1, r2, r3, r4, r5, r6, r7) \
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((r0) | (r1<<4) | (r2<<8) | (r3<<12) | (r4<<16) | (r5<<20) | (r6<<24) | (r7<<28))
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BEGIN_ASM_FUNC setupMpu
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adr r0, _mpu_regions @ Table at end of file
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ldm r0, {r1-r10}
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mcr p15, 0, r1, c6, c0, 0 @ Write MPU region reg 0-7
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mcr p15, 0, r2, c6, c1, 0
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mcr p15, 0, r3, c6, c2, 0
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mcr p15, 0, r4, c6, c3, 0
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mcr p15, 0, r5, c6, c4, 0
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mcr p15, 0, r6, c6, c5, 0
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mcr p15, 0, r7, c6, c6, 0
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mcr p15, 0, r8, c6, c7, 0
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mcr p15, 0, r9, c5, c0, 2 @ Write data access permissions
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mcr p15, 0, r10, c5, c0, 3 @ Write instruction access permissions
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@ Data cachable bits:
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@ Region 0 = no
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@ Region 1 = yes
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@ Region 2 = no <-- Never cache IO regs
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@ Region 3 = yes
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@ Region 4 = yes
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@ Region 5 = no
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@ Region 6 = no
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@ Region 7 = yes
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mov r0, #0b10011010
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mcr p15, 0, r0, c2, c0, 0 @ Data cachable bits
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@ Instruction cachable bits:
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@ Region 0 = no
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@ Region 1 = yes
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@ Region 2 = no
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@ Region 3 = no
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@ Region 4 = no
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@ Region 5 = no
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@ Region 6 = no
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@ Region 7 = yes
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mov r1, #0b10000010
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mcr p15, 0, r1, c2, c0, 1 @ Instruction cachable bits
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@ Write bufferable bits:
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@ Region 0 = no
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@ Region 1 = yes
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@ Region 2 = no <-- Never buffer IO regs
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@ Region 3 = yes
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@ Region 4 = yes
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@ Region 5 = no
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@ Region 6 = no
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@ Region 7 = yes
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@mov r2, #0b10011010 @ Same as data cachable bits
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mcr p15, 0, r0, c3, c0, 0 @ Write bufferable bits
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ldrh r1, =0x1005 @ MPU, D-Cache and I-Cache bitmask
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mrc p15, 0, r0, c1, c0, 0 @ Read control register
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orr r0, r0, r1 @ Enable MPU, D-Cache and I-Cache
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mcr p15, 0, r0, c1, c0, 0 @ Write control register
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bx lr
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.pool
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_mpu_regions:
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@ Region 0: ITCM kernel mirror 32 KiB
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@ Region 1: ARM9 internal mem + N3DS extension 2 MiB
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@ Region 2: IO region 2 MiB covers only ARM9 accessible regs
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@ Region 3: VRAM 8 MiB
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@ Region 4: DSP mem and AXIWRAM 1 MiB
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@ Region 5: FCRAM + N3DS extension 256 MiB
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@ Region 6: DTCM 16 KiB
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@ Region 7: Exception vectors + ARM9 bootrom 64 KiB
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.4byte MAKE_REGION(ITCM_KERNEL_MIRROR, REGION_32KiB)
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.4byte MAKE_REGION(A9_RAM_BASE, REGION_2MiB)
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.4byte MAKE_REGION(IO_MEM_ARM9_ONLY, REGION_2MiB)
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.4byte MAKE_REGION(VRAM_BASE, REGION_8MiB)
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.4byte MAKE_REGION(DSP_MEM_BASE, REGION_1MiB)
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.4byte MAKE_REGION(FCRAM_BASE, REGION_256MiB)
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.4byte MAKE_REGION(DTCM_BASE, REGION_16KiB)
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.4byte MAKE_REGION(BOOT9_BASE, REGION_64KiB)
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_mpu_permissions:
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@ Data access permissions:
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@ Region 0: User = --, Privileged = RW
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@ Region 1: User = --, Privileged = RW
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@ Region 2: User = --, Privileged = RW
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@ Region 3: User = --, Privileged = RW
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@ Region 4: User = --, Privileged = RW
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@ Region 5: User = --, Privileged = RW
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@ Region 6: User = --, Privileged = RW
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@ Region 7: User = --, Privileged = RO
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.4byte MAKE_PERMISSIONS(PER_PRIV_RW_USR_NA, PER_PRIV_RW_USR_NA,
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PER_PRIV_RW_USR_NA, PER_PRIV_RW_USR_NA,
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PER_PRIV_RW_USR_NA, PER_PRIV_RW_USR_NA,
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PER_PRIV_RW_USR_NA, PER_PRIV_RO_USR_NA)
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@ Instruction access permissions:
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@ Region 0: User = --, Privileged = RO
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@ Region 1: User = --, Privileged = RO
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@ Region 2: User = --, Privileged = --
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@ Region 3: User = --, Privileged = --
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@ Region 4: User = --, Privileged = --
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@ Region 5: User = --, Privileged = --
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@ Region 6: User = --, Privileged = --
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@ Region 7: User = --, Privileged = RO
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.4byte MAKE_PERMISSIONS(PER_PRIV_RO_USR_NA, PER_PRIV_RO_USR_NA,
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PER_NA, PER_NA,
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PER_NA, PER_NA,
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PER_NA, PER_PRIV_RO_USR_NA)
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END_ASM_FUNC
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@ Needed by libc
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BEGIN_ASM_FUNC _init, thumb
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC deinitCpu
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mov r3, lr
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msr cpsr_cxsf, #PSR_INT_OFF | PSR_SYS_MODE
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@ Stub vectors to endless loops
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ldr r0, =A9_RAM_BASE
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ldr r2, =MAKE_BRANCH(0, 0) @ Endless loop
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mov r1, #6
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deinitCpu_lp:
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str r2, [r0], #8
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subs r1, r1, #1
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bne deinitCpu_lp
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bl cleanDCache
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mov r2, #0
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ldrh r1, =0x1005 @ MPU, D-Cache and I-Cache bitmask
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mrc p15, 0, r0, c1, c0, 0 @ Read control register
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bic r0, r0, r1 @ Disable MPU, D-Cache and I-Cache
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mcr p15, 0, r0, c1, c0, 0 @ Write control register
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mcr p15, 0, r2, c7, c5, 0 @ Invalidate I-Cache
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mcr p15, 0, r2, c7, c6, 0 @ Invalidate D-Cache
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mcr p15, 0, r2, c7, c10, 4 @ Drain write buffer
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bx r3
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.pool
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END_ASM_FUNC
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