mirror of
https://gitee.com/anod/open_agb_firm.git
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257 lines
6.0 KiB
C
257 lines
6.0 KiB
C
/*
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* This file is part of open_agb_firm
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* Copyright (C) 2021 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "types.h"
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#include "arm11/drivers/i2c.h"
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#include "kevent.h"
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#include "kmutex.h"
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#include "arm11/drivers/interrupt.h"
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static const struct
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{
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u8 busId;
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u8 devAddr;
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} g_i2cDevTable[18] =
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{
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{I2C_BUS1, 0x25u<<1}, // 0x4A
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{I2C_BUS1, 0x3Du<<1}, // 0x7A
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{I2C_BUS1, 0x3Cu<<1}, // 0x78
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{I2C_BUS2, 0x25u<<1}, // 0x4A
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{I2C_BUS2, 0x3Cu<<1}, // 0x78
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{I2C_BUS2, 0x16u<<1}, // 0x2C
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{I2C_BUS2, 0x17u<<1}, // 0x2E
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{I2C_BUS2, 0x20u<<1}, // 0x40
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{I2C_BUS2, 0x22u<<1}, // 0x44
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{I2C_BUS3, 0x6Bu<<1}, // 0xD6
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{I2C_BUS3, 0x68u<<1}, // 0xD0
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{I2C_BUS3, 0x69u<<1}, // 0xD2
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{I2C_BUS3, 0x52u<<1}, // 0xA4
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{I2C_BUS3, 0x4Du<<1}, // 0x9A
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{I2C_BUS3, 0x50u<<1}, // 0xA0
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{I2C_BUS2, 0x77u<<1}, // 0xEE
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{I2C_BUS1, 0x20u<<1}, // 0x40
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{I2C_BUS3, 0x2Au<<1} // 0x54
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};
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typedef struct
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{
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KHandle mutex;
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I2cBus *const i2cBus;
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KHandle event;
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} I2cState;
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static I2cState g_i2cState[3] = {{0, (I2cBus*)I2C1_REGS_BASE, 0},
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{0, (I2cBus*)I2C2_REGS_BASE, 0},
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{0, (I2cBus*)I2C3_REGS_BASE, 0}};
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static bool checkAck(I2cBus *const i2cBus)
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{
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// If we received a NACK stop the transfer.
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if((i2cBus->cnt & I2C_ACK) == 0u)
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{
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i2cBus->cnt = I2C_EN | I2C_IRQ_EN | I2C_ERROR | I2C_STOP;
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return false;
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}
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return true;
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}
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static void sendByte(I2cBus *const i2cBus, u8 data, u8 params, KHandle const event)
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{
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i2cBus->data = data;
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i2cBus->cnt = I2C_EN | I2C_IRQ_EN | I2C_DIR_W | params;
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waitForEvent(event);
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}
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static u8 recvByte(I2cBus *const i2cBus, u8 params, KHandle const event)
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{
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i2cBus->cnt = I2C_EN | I2C_IRQ_EN | I2C_DIR_R | params;
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waitForEvent(event);
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return i2cBus->data;
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}
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void I2C_init(void)
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{
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static bool inited = false;
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if(inited) return;
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inited = true;
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for(u32 i = 0; i < 3; i++)
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{
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static const Interrupt i2cIrqs[3] = {IRQ_I2C1, IRQ_I2C2, IRQ_I2C3};
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const KHandle event = createEvent(true);
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bindInterruptToEvent(event, i2cIrqs[i], 14);
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g_i2cState[i].event = event;
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g_i2cState[i].mutex = createMutex();
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I2cBus *const i2cBus = g_i2cState[i].i2cBus;
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while(i2cBus->cnt & I2C_EN);
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i2cBus->cntex = I2C_CLK_STRETCH;
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i2cBus->scl = I2C_DELAYS(5u, 0u);
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}
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}
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static bool startTransfer(u8 devAddr, u8 regAddr, bool read, const I2cState *const state)
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{
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u32 tries = 8;
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I2cBus *const i2cBus = state->i2cBus;
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const KHandle event = state->event;
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do
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{
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// Edge case on previous transfer error (NACK).
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// This is a special case where we can't predict when or if
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// the IRQ has fired. If it fires after checking but
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// before a wfi this would hang.
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if(i2cBus->cnt & I2C_EN) waitForEvent(event);
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clearEvent(event);
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// Select device and start.
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sendByte(i2cBus, devAddr, I2C_START, event);
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if(!checkAck(i2cBus)) continue;
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// Select register.
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sendByte(i2cBus, regAddr, 0, event);
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if(!checkAck(i2cBus)) continue;
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// Select device in read mode for read transfer.
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if(read)
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{
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sendByte(i2cBus, devAddr | 1u, I2C_START, event);
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if(!checkAck(i2cBus)) continue;
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}
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break;
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} while(--tries > 0);
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return tries > 0;
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}
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bool I2C_readRegBuf(I2cDevice devId, u8 regAddr, u8 *out, u32 size)
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{
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const u8 devAddr = g_i2cDevTable[devId].devAddr;
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const I2cState *const state = &g_i2cState[g_i2cDevTable[devId].busId];
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I2cBus *const i2cBus = state->i2cBus;
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const KHandle event = state->event;
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const KHandle mutex = state->mutex;
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bool res = true;
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lockMutex(mutex);
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if(startTransfer(devAddr, regAddr, true, state))
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{
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while(--size) *out++ = recvByte(i2cBus, I2C_ACK, event);
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// Last byte transfer.
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*out = recvByte(i2cBus, I2C_STOP, event);
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}
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else res = false;
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unlockMutex(mutex);
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return res;
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}
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bool I2C_writeRegBuf(I2cDevice devId, u8 regAddr, const u8 *in, u32 size)
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{
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const u8 devAddr = g_i2cDevTable[devId].devAddr;
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const I2cState *const state = &g_i2cState[g_i2cDevTable[devId].busId];
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I2cBus *const i2cBus = state->i2cBus;
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const KHandle event = state->event;
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const KHandle mutex = state->mutex;
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lockMutex(mutex);
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if(!startTransfer(devAddr, regAddr, false, state))
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{
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unlockMutex(mutex);
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return false;
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}
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while(--size)
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{
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sendByte(i2cBus, *in++, 0, event);
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if(!checkAck(i2cBus))
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{
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unlockMutex(mutex);
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return false;
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}
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}
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// Last byte transfer.
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sendByte(i2cBus, *in, I2C_STOP, event);
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if(!checkAck(i2cBus))
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{
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unlockMutex(mutex);
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return false;
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}
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unlockMutex(mutex);
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return true;
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}
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u8 I2C_readReg(I2cDevice devId, u8 regAddr)
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{
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u8 data;
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if(!I2C_readRegBuf(devId, regAddr, &data, 1)) return 0xFF;
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return data;
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}
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bool I2C_writeReg(I2cDevice devId, u8 regAddr, u8 data)
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{
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return I2C_writeRegBuf(devId, regAddr, &data, 1);
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}
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bool I2C_writeRegIntSafe(I2cDevice devId, u8 regAddr, u8 data)
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{
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const u8 devAddr = g_i2cDevTable[devId].devAddr;
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I2cBus *const i2cBus = getI2cBusRegs(g_i2cDevTable[devId].busId);
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u32 tries = 8;
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do
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{
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while(i2cBus->cnt & I2C_EN);
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// Select device and start.
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i2cBus->data = devAddr;
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i2cBus->cnt = I2C_EN | I2C_DIR_W | I2C_START;
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while(i2cBus->cnt & I2C_EN);
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if(!checkAck(i2cBus)) continue;
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// Select register.
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i2cBus->data = regAddr;
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i2cBus->cnt = I2C_EN | I2C_DIR_W;
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while(i2cBus->cnt & I2C_EN);
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if(!checkAck(i2cBus)) continue;
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break;
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} while(--tries > 0);
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if(tries == 0) return false;
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i2cBus->data = data;
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i2cBus->cnt = I2C_EN | I2C_DIR_W | I2C_STOP;
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while(i2cBus->cnt & I2C_EN);
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if(!checkAck(i2cBus)) return false;
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return true;
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}
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