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325 lines
11 KiB
C
325 lines
11 KiB
C
#pragma once
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/*
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* This file is part of open_agb_firm
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* Copyright (C) 2021 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if !__ASSEMBLER__
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#include "types.h"
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#endif
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// Program status register (CPSR/SPSR)
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#define PSR_USER_MODE (16)
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#define PSR_FIQ_MODE (17)
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#define PSR_IRQ_MODE (18)
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#define PSR_SVC_MODE (19)
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#define PSR_ABORT_MODE (23)
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#define PSR_UNDEF_MODE (27)
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#define PSR_SYS_MODE (31)
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#define PSR_MODE_MASK (PSR_SYS_MODE)
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#define PSR_T (1<<5) // Thumb mode
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#define PSR_F (1<<6) // Interrupts (FIQ) disable flag
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#define PSR_I (1<<7) // Interrupts (IRQ) disable flag
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#define PSR_A (1<<8) // Imprecise aborts disable flag
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#define PSR_E (1<<9) // Big endian
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#define PSR_J (1<<24) // Jazelle mode
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#define PSR_Q (1<<27)
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#define PSR_V (1<<28) // Overflow flag
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#define PSR_C (1<<29) // Carry flag
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#define PSR_Z (1<<30) // Zero flag
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#define PSR_N (1<<31) // Negative flag
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#define PSR_INT_OFF (PSR_I | PSR_F) // IRQ and FIQ disabled flags
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#if !__ASSEMBLER__
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#define MAKE_INTR_NO_INOUT(isVolatile, name, inst, ...) \
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ALWAYS_INLINE void __##name(void) \
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{ \
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if(isVolatile == 1) \
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__asm__ volatile(inst : : : __VA_ARGS__); \
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else \
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__asm__(inst : : : __VA_ARGS__); \
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}
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#define MAKE_INTR_GET_REG(isVolatile, name, inst) \
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ALWAYS_INLINE u32 __##name(void) \
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{ \
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u32 reg; \
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if(isVolatile == 1) \
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__asm__ volatile(inst : "=r" (reg) : : ); \
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else \
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__asm__(inst : "=r" (reg) : : ); \
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return reg; \
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}
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#define MAKE_INTR_SET_REG_ZERO(isVolatile, name, inst, ...) \
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ALWAYS_INLINE void __##name(void) \
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{ \
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if(isVolatile == 1) \
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__asm__ volatile(inst : : "r" (0) : __VA_ARGS__); \
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else \
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__asm__(inst : : "r" (0) : __VA_ARGS__); \
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}
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#define MAKE_INTR_SET_REG(isVolatile, name, inst, ...) \
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ALWAYS_INLINE void __##name(u32 reg) \
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{ \
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if(isVolatile == 1) \
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__asm__ volatile(inst : : "r" (reg) : __VA_ARGS__); \
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else \
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__asm__(inst : : "r" (reg) : __VA_ARGS__); \
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}
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#define __bkpt(val) __asm__ volatile("bkpt #" #val : : : )
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#if !__thumb__
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// Program status register
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MAKE_INTR_GET_REG(1, getCpsr, "mrs %0, cpsr")
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MAKE_INTR_SET_REG(1, setCpsr_c, "msr cpsr_c, %0", "memory")
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MAKE_INTR_SET_REG(1, setCpsr, "msr cpsr_cxsf, %0", "memory")
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MAKE_INTR_GET_REG(1, getSpsr, "mrs %0, spsr")
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MAKE_INTR_SET_REG(1, setSpsr_c, "msr spsr_c, %0", "memory")
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MAKE_INTR_SET_REG(1, setSpsr, "msr spsr_cxsf, %0", "memory")
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// Control Register
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MAKE_INTR_GET_REG(1, getCr, "mrc p15, 0, %0, c1, c0, 0")
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MAKE_INTR_SET_REG(1, setCr, "mcr p15, 0, %0, c1, c0, 0", "memory")
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#endif // if !__thumb__
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#ifdef ARM11
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#define __cpsid(flags) __asm__ volatile("cpsid " #flags : : : "memory")
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#define __cpsie(flags) __asm__ volatile("cpsie " #flags : : : "memory")
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#define __setend(end) __asm__ volatile("setend " #end : : : "memory")
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MAKE_INTR_NO_INOUT(1, nop, "nop")
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MAKE_INTR_NO_INOUT(1, wfi, "wfi", "memory")
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MAKE_INTR_NO_INOUT(1, wfe, "wfe", "memory")
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MAKE_INTR_NO_INOUT(1, sev, "sev")
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#if !__thumb__
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ALWAYS_INLINE u8 __ldrexb(vu8 *addr)
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{
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u8 res;
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__asm__ volatile("ldrexb %0, %1" : "=r" (res) : "Q" (*addr) : );
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return res;
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}
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ALWAYS_INLINE u16 __ldrexh(vu16 *addr)
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{
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u16 res;
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__asm__ volatile("ldrexh %0, %1" : "=r" (res) : "Q" (*addr) : );
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return res;
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}
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ALWAYS_INLINE u32 __ldrex(vu32 *addr)
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{
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u32 res;
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__asm__ volatile("ldrex %0, %1" : "=r" (res) : "Q" (*addr) : );
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return res;
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}
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/*ALWAYS_INLINE u64 __ldrexd(vu64 *addr)
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{
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union
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{
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u32 r32[2];
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u64 r64;
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} r;
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// TODO: "Error: even register required -- `ldrexd r3,r2,[r0]'"
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#ifndef __ARMEB__ // Little endian
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__asm__ volatile("ldrexd %0, %1, %2" : "=r" (r.r32[0]), "=r" (r.r32[1]) : "Q" (*addr) : );
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#else // Big endian
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__asm__ volatile("ldrexd %0, %1, %2" : "=r" (r.r32[1]), "=r" (r.r32[0]) : "Q" (*addr) : );
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#endif
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return r.r64;
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}*/
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ALWAYS_INLINE u32 __strexb(vu8 *addr, u8 val)
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{
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u32 res;
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__asm__ volatile("strexb %0, %2, %1" : "=&r" (res), "=Q" (*addr) : "r" (val) : );
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return res;
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}
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ALWAYS_INLINE u32 __strexh(vu16 *addr, u16 val)
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{
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u32 res;
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__asm__ volatile("strexh %0, %2, %1" : "=&r" (res), "=Q" (*addr) : "r" (val) : );
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return res;
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}
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ALWAYS_INLINE u32 __strex(vu32 *addr, u32 val)
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{
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u32 res;
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__asm__ volatile("strex %0, %2, %1" : "=&r" (res), "=Q" (*addr) : "r" (val) : );
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return res;
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}
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/*ALWAYS_INLINE u32 __strexd(vu64 *addr, u64 val)
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{
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union
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{
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u32 r32[2];
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u64 r64;
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} r;
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r.r64 = val;
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// TODO: "Error: even register required -- `strexd r0,r3,r2,[r1]'"
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u32 res;
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#ifndef __ARMEB__ // Little endian
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__asm__ volatile("strexd %0, %2, %3, %1" : "=&r" (res), "=Q" (*addr) : "r" (r.r32[0]), "r" (r.r32[1]) : );
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#else // Big endian
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__asm__ volatile("strexd %0, %2, %3, %1" : "=&r" (res), "=Q" (*addr) : "r" (r.r32[1]), "r" (r.r32[0]) : );
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#endif
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return res;
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}*/
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MAKE_INTR_NO_INOUT(1, clrex, "clrex", "memory")
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// Debug ID Register
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MAKE_INTR_GET_REG(0, getDidr, "mrc p14, 0, %0, c0, c0, 0")
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// Debug Status and Control Register
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MAKE_INTR_GET_REG(1, getDscr, "mrc p14, 0, %0, c0, c1, 0")
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MAKE_INTR_SET_REG(1, setDscr, "mcr p14, 0, %0, c0, c1, 0", "memory")
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// Data Transfer Register
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// Vector Catch Register
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MAKE_INTR_GET_REG(1, getVcr, "mrc p14, 0, %0, c0, c7, 0")
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MAKE_INTR_SET_REG(1, setVcr, "mcr p14, 0, %0, c0, c7, 0", "memory")
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// Breakpoint Value Register 0-5
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MAKE_INTR_GET_REG(1, getBvr0, "mrc p14, 0, %0, c0, c0, 4")
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MAKE_INTR_SET_REG(1, setBvr0, "mcr p14, 0, %0, c0, c0, 4", "memory")
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MAKE_INTR_GET_REG(1, getBvr1, "mrc p14, 0, %0, c0, c1, 4")
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MAKE_INTR_SET_REG(1, setBvr1, "mcr p14, 0, %0, c0, c1, 4", "memory")
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MAKE_INTR_GET_REG(1, getBvr2, "mrc p14, 0, %0, c0, c2, 4")
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MAKE_INTR_SET_REG(1, setBvr2, "mcr p14, 0, %0, c0, c2, 4", "memory")
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MAKE_INTR_GET_REG(1, getBvr3, "mrc p14, 0, %0, c0, c3, 4")
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MAKE_INTR_SET_REG(1, setBvr3, "mcr p14, 0, %0, c0, c3, 4", "memory")
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MAKE_INTR_GET_REG(1, getBvr4, "mrc p14, 0, %0, c0, c4, 4")
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MAKE_INTR_SET_REG(1, setBvr4, "mcr p14, 0, %0, c0, c4, 4", "memory")
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MAKE_INTR_GET_REG(1, getBvr5, "mrc p14, 0, %0, c0, c5, 4")
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MAKE_INTR_SET_REG(1, setBvr5, "mcr p14, 0, %0, c0, c5, 4", "memory")
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// Breakpoint Control Register 0-5
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MAKE_INTR_GET_REG(1, getBcr0, "mrc p14, 0, %0, c0, c0, 5")
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MAKE_INTR_SET_REG(1, setBcr0, "mcr p14, 0, %0, c0, c0, 5", "memory")
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MAKE_INTR_GET_REG(1, getBcr1, "mrc p14, 0, %0, c0, c1, 5")
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MAKE_INTR_SET_REG(1, setBcr1, "mcr p14, 0, %0, c0, c1, 5", "memory")
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MAKE_INTR_GET_REG(1, getBcr2, "mrc p14, 0, %0, c0, c2, 5")
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MAKE_INTR_SET_REG(1, setBcr2, "mcr p14, 0, %0, c0, c2, 5", "memory")
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MAKE_INTR_GET_REG(1, getBcr3, "mrc p14, 0, %0, c0, c3, 5")
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MAKE_INTR_SET_REG(1, setBcr3, "mcr p14, 0, %0, c0, c3, 5", "memory")
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MAKE_INTR_GET_REG(1, getBcr4, "mrc p14, 0, %0, c0, c4, 5")
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MAKE_INTR_SET_REG(1, setBcr4, "mcr p14, 0, %0, c0, c4, 5", "memory")
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MAKE_INTR_GET_REG(1, getBcr5, "mrc p14, 0, %0, c0, c5, 5")
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MAKE_INTR_SET_REG(1, setBcr5, "mcr p14, 0, %0, c0, c5, 5", "memory")
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// Watchpoint Value Register 0-1
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MAKE_INTR_GET_REG(1, getWvr0, "mrc p14, 0, %0, c0, c0, 6")
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MAKE_INTR_SET_REG(1, setWvr0, "mcr p14, 0, %0, c0, c0, 6", "memory")
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MAKE_INTR_GET_REG(1, getWvr1, "mrc p14, 0, %0, c0, c1, 6")
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MAKE_INTR_SET_REG(1, setWvr1, "mcr p14, 0, %0, c0, c1, 6", "memory")
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// Watchpoint Control Register 0-1
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MAKE_INTR_GET_REG(1, getWcr0, "mrc p14, 0, %0, c0, c0, 7")
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MAKE_INTR_SET_REG(1, setWcr0, "mcr p14, 0, %0, c0, c0, 7", "memory")
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MAKE_INTR_GET_REG(1, getWcr1, "mrc p14, 0, %0, c0, c1, 7")
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MAKE_INTR_SET_REG(1, setWcr1, "mcr p14, 0, %0, c0, c1, 7", "memory")
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ALWAYS_INLINE u32 __getCpuId(void)
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{
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u32 cpuId;
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__asm__("mrc p15, 0, %0, c0, c0, 5" : "=r" (cpuId) : );
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return cpuId & 3;
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}
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// Auxiliary Control Register
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MAKE_INTR_GET_REG(1, getAcr, "mrc p15, 0, %0, c1, c0, 1")
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MAKE_INTR_SET_REG(1, setAcr, "mcr p15, 0, %0, c1, c0, 1", "memory")
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// Translation Table Base Register 0
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MAKE_INTR_GET_REG(1, getTtbr0, "mrc p15, 0, %0, c2, c0, 0")
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MAKE_INTR_SET_REG(1, setTtbr0, "mcr p15, 0, %0, c2, c0, 0", "memory")
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// Translation Table Base Register 1
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MAKE_INTR_GET_REG(1, getTtbr1, "mrc p15, 0, %0, c2, c0, 1")
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MAKE_INTR_SET_REG(1, setTtbr1, "mcr p15, 0, %0, c2, c0, 1", "memory")
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// Translation Table Base Control Register
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MAKE_INTR_GET_REG(1, getTtbcr, "mrc p15, 0, %0, c2, c0, 2")
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MAKE_INTR_SET_REG(1, setTtbcr, "mcr p15, 0, %0, c2, c0, 2", "memory")
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// Domain Access Control Register
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MAKE_INTR_GET_REG(1, getDacr, "mrc p15, 0, %0, c3, c0, 0")
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MAKE_INTR_SET_REG(1, setDacr, "mcr p15, 0, %0, c3, c0, 0", "memory")
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// Data Fault Status Register
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MAKE_INTR_GET_REG(1, getDfsr, "mrc p15, 0, %0, c5, c0, 0")
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MAKE_INTR_SET_REG(1, setDfsr, "mcr p15, 0, %0, c5, c0, 0", "memory")
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// Instruction Fault Status Register
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MAKE_INTR_GET_REG(1, getIfsr, "mrc p15, 0, %0, c5, c0, 1")
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MAKE_INTR_SET_REG(1, setIfsr, "mcr p15, 0, %0, c5, c0, 1", "memory")
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// Fault Address Register
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MAKE_INTR_GET_REG(1, getFar, "mrc p15, 0, %0, c6, c0, 0")
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MAKE_INTR_SET_REG(1, setFar, "mcr p15, 0, %0, c6, c0, 0", "memory")
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// Watchpoint Fault Address Register
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MAKE_INTR_GET_REG(1, getWfar, "mrc p15, 0, %0, c6, c0, 1")
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MAKE_INTR_SET_REG(1, setWfar, "mcr p15, 0, %0, c6, c0, 1", "memory")
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// Flush Prefetch Buffer
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// Data Synchronization Barrier
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// Data Memory Barrier
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MAKE_INTR_SET_REG_ZERO(1, isb, "mcr p15, 0, %0, c7, c5, 4", "memory")
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MAKE_INTR_SET_REG_ZERO(1, dsb, "mcr p15, 0, %0, c7, c10, 4", "memory")
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MAKE_INTR_SET_REG_ZERO(1, dmb, "mcr p15, 0, %0, c7, c10, 5", "memory")
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// FCSE PID Register
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MAKE_INTR_GET_REG(1, getFcsepidr, "mrc p15, 0, %0, c13, c0, 0")
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MAKE_INTR_SET_REG(1, setFcsepidr, "mcr p15, 0, %0, c13, c0, 0", "memory")
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// Context ID Register
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MAKE_INTR_GET_REG(1, getCidr, "mrc p15, 0, %0, c13, c0, 1")
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MAKE_INTR_SET_REG(1, setCidr, "mcr p15, 0, %0, c13, c0, 1", "memory")
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#endif // if !__thumb__
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#elif ARM9
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#if !__thumb__
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MAKE_INTR_NO_INOUT(1, wfi, "mcr p15, 0, r0, c7, c0, 4", "memory")
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#endif // if !__thumb__
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#endif // ifdef ARM11
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#undef MAKE_INTR_NO_INOUT
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#undef MAKE_INTR_GET_REG
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#undef MAKE_INTR_SET_REG_ZERO
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#undef MAKE_INTR_SET_REG
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#endif // if !__ASSEMBLER__
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