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78da297199
gfx: 常量大改名、函数大改名，增加了双缓冲的一些驱动函数 其他：基本是ARM9/ARM11宏修改和BIT取值修改，bool从c风格转成c++强类型风格等。sha.c使用了memory.h进行的改动(copy32)
429 lines
19 KiB
C
429 lines
19 KiB
C
#pragma once
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/*
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* This file is part of libn3ds
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* Copyright (C) 2024 profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "types.h"
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#include "mem_map.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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// For simplicity we will name the accessible 2 controllers 1 and 2.
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// The real controller number is in the comment.
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#ifdef __ARM9__
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#define TMIO1_REGS_BASE (IO_AHB_BASE + 0x6000) // Controller 1.
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#define TMIO2_REGS_BASE (IO_AHB_BASE + 0x7000) // Controller 3. Remappable.
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#elif __ARM11__
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#define TMIO1_REGS_BASE (IO_COMMON_BASE + 0x22000) // Controller 2.
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#define TMIO2_REGS_BASE (IO_COMMON_BASE) // Controller 3. Remappable.
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#endif // #ifdef __ARM9__
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#define TMIO_HCLK (67027964u) // In Hz.
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typedef struct
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{
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vu16 sd_cmd; // 0x000
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vu16 sd_portsel; // 0x002
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vu32 sd_arg; // 0x004 SD_ARG0 and SD_ARG1 combined.
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vu16 sd_stop; // 0x008
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vu16 sd_blockcount; // 0x00A
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const vu32 sd_resp[4]; // 0x00C SD_RESP0-7 16 bit reg pairs combined.
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vu32 sd_status; // 0x01C SD_STATUS1 and SD_STATUS2 combined.
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vu32 sd_status_mask; // 0x020 SD_STATUS1_MASK and SD_STATUS2_MASK combined.
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vu16 sd_clk_ctrl; // 0x024
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vu16 sd_blocklen; // 0x026
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vu16 sd_option; // 0x028 Card detect timer, data timeout and bus width.
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u8 _0x2a[2];
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const vu32 sd_err_status; // 0x02C SD_ERR_STATUS1 and SD_ERR_STATUS2 combined.
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vu16 sd_fifo; // 0x030
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u8 _0x32[2];
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vu16 sdio_mode; // 0x034
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vu16 sdio_status; // 0x036
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vu16 sdio_status_mask; // 0x038
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u8 _0x3a[0x9e];
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vu16 dma_ext_mode; // 0x0D8
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u8 _0xda[6];
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vu16 soft_rst; // 0x0E0
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const vu16 revision; // 0x0E2 Controller version/revision?
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u8 _0xe4[0xe];
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vu16 unkF2; // 0x0F2 Power related? Default 0. Other values do nothing?
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vu16 ext_sdio_irq; // 0x0F4 Port 1/2/3 SDIO IRQ control.
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const vu16 ext_wrprot; // 0x0F6 Apparently for eMMC.
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vu16 ext_cdet; // 0x0F8 Card detect status.
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vu16 ext_cdet_dat3; // 0x0FA DAT3 card detect status.
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vu16 ext_cdet_mask; // 0x0FC Card detect mask (IRQ).
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vu16 ext_cdet_dat3_mask; // 0x0FE DAT3 card detect mask (IRQ).
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vu16 sd_fifo32_cnt; // 0x100
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u8 _0x102[2];
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vu16 sd_blocklen32; // 0x104
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u8 _0x106[2];
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vu16 sd_blockcount32; // 0x108
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u8 _0x10a[2];
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vu32 sd_fifo32; // 0x10C Note: This is in the FIFO region on ARM11 (3DS).
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} Tmio;
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static_assert(offsetof(Tmio, sd_fifo32) == 0x10C, "Error: Member sd_fifo32 of Tmio is not at offset 0x10C!");
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ALWAYS_INLINE Tmio* getTmioRegs(const u8 controller)
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{
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return (controller == 0 ? (Tmio*)TMIO1_REGS_BASE : (Tmio*)TMIO2_REGS_BASE);
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}
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ALWAYS_INLINE vu32* getTmioFifo(Tmio *const regs)
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{
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#ifdef __ARM11__
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return (vu32*)((uintptr_t)regs + 0x200000); // FIFO is in the DMA region.
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#else
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return ®s->sd_fifo32;
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#endif // #ifdef __ARM11__
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}
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// REG_SD_CMD
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// Auto response supported commands:
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// CMD0, CMD2, CMD3 (only SD?), CMD7 (only select?), CMD9, CMD10, CMD12, CMD13,
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// CMD16, CMD17, CMD18, CMD25, CMD28, CMD55, ACMD6, ACMD23, ACMD42, ACMD51.
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//
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// When using auto response leave bits 11-13 unset (zero).
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// Bit 0-5 command index.
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#define CMD_ACMD BIT(6) // Application command.
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#define CMD_RESP_AUTO (0u) // Response type auto. Only works with certain commands.
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#define CMD_RESP_NONE (3u<<8) // Response type none.
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#define CMD_RESP_R1 (4u<<8) // Response type R1 48 bit.
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#define CMD_RESP_R5 (CMD_RESP_R1) // Response type R5 48 bit.
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#define CMD_RESP_R6 (CMD_RESP_R1) // Response type R6 48 bit.
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#define CMD_RESP_R7 (CMD_RESP_R1) // Response type R7 48 bit.
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#define CMD_RESP_R1b (5u<<8) // Response type R1b 48 bit + busy.
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#define CMD_RESP_R5b (CMD_RESP_R1b) // Response type R5b 48 bit + busy.
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#define CMD_RESP_R2 (6u<<8) // Response type R2 136 bit.
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#define CMD_RESP_R3 (7u<<8) // Response type R3 48 bit OCR without CRC.
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#define CMD_RESP_R4 (CMD_RESP_R3) // Response type R4 48 bit OCR without CRC.
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#define CMD_RESP_MASK (CMD_RESP_R3)
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#define CMD_DATA_EN BIT(11) // Data transfer enable.
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#define CMD_DATA_R BIT(12) // Data transfer direction read.
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#define CMD_DATA_W (0u) // Data transfer direction write.
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#define CMD_MULTI_DATA BIT(13) // Multi block transfer (auto STOP_TRANSMISSION).
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#define CMD_SEC_SDIO BIT(14) // Security/SDIO command.
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// REG_SD_PORTSEL
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#define PORTSEL_P0 (0u) // Controller port 0.
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#define PORTSEL_P1 (1u) // Controller port 1.
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#define PORTSEL_P2 (2u) // Controller port 2.
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#define PORTSEL_P3 (3u) // Controller port 3.
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#define PORTSEL_MASK (PORTSEL_P3)
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// Bit 8-9 number of supported ports?
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#define PORTSEL_UNK10 BIT(10) // Unknown writable bit 10?
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// REG_SD_STOP
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#define STOP_STOP BIT(0) // Abort data transfer and send STOP_TRANSMISSION CMD.
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#define STOP_AUTO_STOP BIT(8) // Automatically send STOP_TRANSMISSION on multi-block transfer end.
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// REG_SD_STATUS1/2 Write 0 to acknowledge a bit.
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// REG_SD_STATUS1/2_MASK (M) = Maskable bit. 1 = disabled.
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// Unmaskable bits act as status only, don't trigger IRQs and can't be acknowledged.
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#define STATUS_RESP_END BIT(0) // (M) Response end.
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#define STATUS_DATA_END BIT(2) // (M) Data transfer end (triggers after last block).
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#define STATUS_REMOVE BIT(3) // (M) Card got removed.
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#define STATUS_INSERT BIT(4) // (M) Card got inserted. Set at the same time as DETECT.
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#define STATUS_DETECT BIT(5) // Card detect status (SD_OPTION detection timer). 1 = inserted.
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#define STATUS_NO_WRPROT BIT(7) // Write protection slider unlocked (low).
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#define STATUS_DAT3_REMOVE BIT(8) // (M) Card DAT3 got removed (low).
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#define STATUS_DAT3_INSERT BIT(9) // (M) Card DAT3 got inserted (high).
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#define STATUS_DAT3_DETECT BIT(10) // Card DAT3 status. 1 = inserted.
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#define STATUS_ERR_CMD_IDX BIT(16) // (M) Bad CMD index in response.
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#define STATUS_ERR_CRC BIT(17) // (M) Bad CRC in response.
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#define STATUS_ERR_STOP_BIT BIT(18) // (M) Stop bit error. Failed to recognize response frame end?
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#define STATUS_ERR_DATA_TIMEOUT BIT(19) // (M) Response data timeout.
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#define STATUS_ERR_RX_OVERF BIT(20) // (M) Receive FIFO overflow.
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#define STATUS_ERR_TX_UNDERF BIT(21) // (M) Send FIFO underflow.
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#define STATUS_ERR_CMD_TIMEOUT BIT(22) // (M) Response start bit timeout.
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#define STATUS_SD_BUSY BIT(23) // SD card signals busy if this bit is 0 (DAT0 held low).
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#define STATUS_RX_RDY BIT(24) // (M) FIFO ready for read.
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#define STATUS_TX_REQ BIT(25) // (M) FIFO write request.
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// Bit 27 is maskable. Purpose unknown.
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// Bit 29 exists (not maskable). Signals when clock divider changes are allowed?
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#define STATUS_CMD_BUSY BIT(30) // Command register busy.
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#define STATUS_ERR_ILL_ACC BIT(31) // (M) Illegal access error. TODO: What does that mean?
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#define STATUS_MASK_ALL (0xFFFFFFFFu)
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#define STATUS_MASK_DEFAULT (BIT(27) | STATUS_TX_REQ | STATUS_RX_RDY | \
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STATUS_DAT3_INSERT | STATUS_DAT3_REMOVE)
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#define STATUS_MASK_ERR (STATUS_ERR_ILL_ACC | STATUS_ERR_CMD_TIMEOUT | STATUS_ERR_TX_UNDERF | \
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STATUS_ERR_RX_OVERF | STATUS_ERR_DATA_TIMEOUT | STATUS_ERR_STOP_BIT | \
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STATUS_ERR_CRC | STATUS_ERR_CMD_IDX)
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// REG_SD_CLK_CTRL
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#define SD_CLK_DIV_2 (0u) // Clock divider 2.
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#define SD_CLK_DIV_4 BIT(0) // Clock divider 4.
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#define SD_CLK_DIV_8 BIT(1) // Clock divider 8.
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#define SD_CLK_DIV_16 BIT(2) // Clock divider 16.
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#define SD_CLK_DIV_32 BIT(3) // Clock divider 32.
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#define SD_CLK_DIV_64 BIT(4) // Clock divider 64.
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#define SD_CLK_DIV_128 BIT(5) // Clock divider 128.
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#define SD_CLK_DIV_256 BIT(6) // Clock divider 256.
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#define SD_CLK_DIV_512 BIT(7) // Clock divider 512.
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#define SD_CLK_EN BIT(8) // Clock enable.
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#define SD_CLK_PWR_SAVE BIT(9) // Disables clock on idle.
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// Bit 10 is writable... at least according to gbatek (can't confirm). Purpose unknown.
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// Outputs the matching divider for clk.
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// Shift the output right by 2 to get the value for REG_SD_CLK_CTRL.
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ALWAYS_INLINE u32 TMIO_clk2div(const u32 clk)
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{
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u32 shift = 1;
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while(clk < TMIO_HCLK>>shift) ++shift;
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return BIT(shift);
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}
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// Clock off by default.
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// Nearest possible for 400 kHz is 261.827984375 kHz.
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#define SD_CLK_DEFAULT (TMIO_clk2div(400000)>>2)
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// REG_SD_OPTION
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// Note on card detection time:
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// The card detection timer starts only on inserting cards (including cold boot with inserted card)
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// and when mapping ports between controllers. Card power doesn't have any effect on the timer.
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//
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// Bit 0-3 card detect timer 0x400<<x HCLKs. 0xF timer test (0x100 HCLKs).
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// Bit 4-7 data timeout 0x2000<<x SDCLKs. 0xF timeout test (0x100 SDCLKs).
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#define OPTION_UNK14 BIT(14) // "no C2 module" What the fuck is a C2 module?
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#define OPTION_BUS_WIDTH4 (0u) // 4 bit bus width.
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#define OPTION_BUS_WIDTH1 BIT(15) // 1 bit bus width.
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// Card detect time: 0x400<<9 / 67027964 = 0.007821929 seconds.
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// Data timeout: 0x2000<<12 / (67027964 / 2) = 1.001206959 seconds.
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#define OPTION_DEFAULT_TIMINGS (12u<<4 | 9u)
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// REG_SD_ERR_STATUS1/2 Write 0 to acknowledge a bit.
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// TODO: Are all of these actually supported on this controller?
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#define ERR_RESP_CMD_IDX BIT(0) // Manual command index error in response.
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#define ERR_RESP_CMD12_IDX BIT(1) // Auto command index error in response.
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#define ERR_RESP_STOP_BIT BIT(2) // Manual command response stop bit error.
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#define ERR_RESP_STOP_BIT_CMD12 BIT(3) // Auto command response stop bit error.
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#define ERR_STOP_BIT_DATA_READ BIT(4) // Stop bit error in read data.
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#define ERR_STOP_BIT_WR_CRC BIT(5) // Stop bit error for write CRC status. What the hell does that mean?
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#define ERR_CMD_RESP_CRC BIT(8) // Manual command response CRC error.
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#define ERR_CMD12_RESP_CRC BIT(9) // Auto command response CRC error.
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#define ERR_DATA_READ_CRC BIT(10) // CRC error for read data.
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#define ERR_WR_CRC_STAT BIT(11) // "CRC error for Write CRC status for a write command". What the hell does that mean?
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// Bit 13 always 1.
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#define ERR_CMD_RESP_TMOUT BIT(16) // Manual command response timeout.
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#define ERR_CMD12_RESP_TMOUT BIT(17) // Auto command response timeout.
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// TODO: Add the correct remaining ones.
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// REG_SDIO_MODE
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#define SDIO_MODE_SDIO_IRQ_EN BIT(0) // SDIO IRQ enable (DAT1 low).
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#define SDIO_MODE_UNK2_EN BIT(2) // IRQ on "read wait" requests?
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#define SDIO_MODE_UNK8 BIT(8) // Aborts command and data transfer?
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#define SDIO_MODE_UNK9 BIT(9) // Aborts command but not data transfer? CMD52 related.
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// REG_SDIO_STATUS Write 0 to acknowledge a bit.
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// REG_SDIO_STATUS_MASK (M) = Maskable bit. 1 = disabled.
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#define SDIO_STATUS_SDIO_IRQ BIT(0) // (M) SDIO IRQ (DAT1 low).
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#define SDIO_STATUS_UNK1_IRQ BIT(1) // (M) IRQ once CMD52 can be used after abort?
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#define SDIO_STATUS_UNK2_IRQ BIT(2) // (M) Related to SDIO_MODE_UNK2_EN?
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#define SDIO_STATUS_UNK14_IRQ BIT(14) // (M) Related to SDIO_MODE_UNK9?
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#define SDIO_STATUS_UNK15_IRQ BIT(15) // (M) Related to SDIO_MODE_UNK2_EN?
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#define SDIO_STATUS_MASK_ALL (0xFFFFu)
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// REG_DMA_EXT_MODE
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#define DMA_EXT_CPU_MODE (0u) // Disables DMA requests. Actually also turns off the 32 bit FIFO.
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#define DMA_EXT_DMA_MODE BIT(1) // Enables DMA requests.
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#define DMA_EXT_UNK5 BIT(5) // "Buffer status mode"?
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// REG_SOFT_RST
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#define SOFT_RST_RST (0u) // Reset.
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#define SOFT_RST_NORST BIT(0) // No reset.
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// REG_EXT_SDIO_IRQ
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#define EXT_SDIO_IRQ_P1 BIT(0) // Port 1 SDIO IRQ (DAT1 low). Write 0 to acknowledge.
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#define EXT_SDIO_IRQ_P2 BIT(1) // Port 2 SDIO IRQ (DAT1 low). Write 0 to acknowledge.
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#define EXT_SDIO_IRQ_P3 BIT(2) // Port 3 SDIO IRQ (DAT1 low). Write 0 to acknowledge.
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#define EXT_SDIO_IRQ_P1_EN BIT(4) // Port 1 SDIO IRQ enable (controller).
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#define EXT_SDIO_IRQ_P2_EN BIT(5) // Port 2 SDIO IRQ enable (controller).
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#define EXT_SDIO_IRQ_P3_EN BIT(6) // Port 3 SDIO IRQ enable (controller).
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#define EXT_SDIO_IRQ_P1_MASK BIT(8) // Port 1 SDIO IRQ mask. 1 = disable IRQ (CPU).
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#define EXT_SDIO_IRQ_P2_MASK BIT(9) // Port 2 SDIO IRQ mask. 1 = disable IRQ (CPU).
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#define EXT_SDIO_IRQ_P3_MASK BIT(10) // Port 3 SDIO IRQ mask. 1 = disable IRQ (CPU).
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#define EXT_SDIO_IRQ_MASK_ALL (EXT_SDIO_IRQ_P3_MASK | EXT_SDIO_IRQ_P2_MASK | EXT_SDIO_IRQ_P1_MASK)
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// REG_EXT_WRPROT Each bit 1 = write protected unlike SD_STATUS.
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#define EXT_WRPROT_P1 BIT(0)
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#define EXT_WRPROT_P2 BIT(1)
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#define EXT_WRPROT_P3 BIT(2)
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// REG_EXT_CDET Acknowledgeable?
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// REG_EXT_CDET_MASK (M) = Maskable bit. 1 = disabled (no IRQ).
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#define EXT_CDET_P1_REMOVE BIT(0) // (M) Port 1 card got removed.
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#define EXT_CDET_P1_INSERT BIT(1) // (M) Port 1 card got inserted. TODO: With detection timer?
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#define EXT_CDET_P1_DETECT BIT(2) // Port 1 card detect status. 1 = inserted. TODO: With detection timer?
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#define EXT_CDET_P2_REMOVE BIT(3) // (M) Port 2 card got removed.
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#define EXT_CDET_P2_INSERT BIT(4) // (M) Port 2 card got inserted. TODO: With detection timer?
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#define EXT_CDET_P2_DETECT BIT(5) // Port 2 card detect status. 1 = inserted. TODO: With detection timer?
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#define EXT_CDET_P3_REMOVE BIT(6) // (M) Port 3 card got removed.
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#define EXT_CDET_P3_INSERT BIT(7) // (M) Port 3 card got inserted. TODO: With detection timer?
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#define EXT_CDET_P3_DETECT BIT(8) // Port 3 card detect status. 1 = inserted. TODO: With detection timer?
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#define EXT_CDET_MASK_ALL (0xFFFFu)
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// REG_EXT_CDET_DAT3 Acknowledgeable?
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// REG_EXT_CDET_DAT3_MASK (M) = Maskable bit. 1 = disabled (no IRQ).
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#define EXT_CDET_DAT3_P1_REMOVE BIT(0) // (M) Port 1 card DAT3 got removed (low).
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#define EXT_CDET_DAT3_P1_INSERT BIT(1) // (M) Port 1 card DAT3 got inserted (high).
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#define EXT_CDET_DAT3_P1_DETECT BIT(2) // Port 1 card DAT3 status. 1 = inserted.
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#define EXT_CDET_DAT3_P2_REMOVE BIT(3) // (M) Port 2 card DAT3 got removed (low).
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#define EXT_CDET_DAT3_P2_INSERT BIT(4) // (M) Port 2 card DAT3 got inserted (high).
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#define EXT_CDET_DAT3_P2_DETECT BIT(5) // Port 2 card DAT3 status. 1 = inserted.
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#define EXT_CDET_DAT3_P3_REMOVE BIT(6) // (M) Port 3 card DAT3 got removed (low).
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#define EXT_CDET_DAT3_P3_INSERT BIT(7) // (M) Port 3 card DAT3 got inserted (high).
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#define EXT_CDET_DAT3_P3_DETECT BIT(8) // Port 3 card DAT3 status. 1 = inserted.
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#define EXT_CDET_DAT3_MASK_ALL (0xFFFFu)
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// REG_SD_FIFO32_CNT
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// Bit 0 unknown, non-writable.
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#define FIFO32_EN BIT(1) // Enables the 32 bit FIFO.
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#define FIFO32_FULL BIT(8) // FIFO is full.
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#define FIFO32_NOT_EMPTY BIT(9) // FIFO is not empty. Inverted bit. 0 means empty.
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#define FIFO32_CLEAR BIT(10) // Clears the FIFO.
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#define FIFO32_FULL_IE BIT(11) // FIFO full IRQ enable.
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#define FIFO32_NOT_EMPTY_IE BIT(12) // FIFO not empty IRQ enable.
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typedef struct
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{
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u8 portNum;
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u16 sd_clk_ctrl;
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u16 sd_blocklen; // Also sd_blocklen32.
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u16 sd_option;
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void *buf;
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u16 blocks;
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u32 resp[4]; // Little endian, MSB first.
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} TmioPort;
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/**
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* @brief Initializes the tmio driver. For libn3ds internal usage only.
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*/
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void TMIO_init(void);
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/**
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* @brief Deinitializes the tmio driver. For libn3ds internal usage only.
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*/
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void TMIO_deinit(void);
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/**
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* @brief Initializes a tmio port to defaults.
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*
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* @param port A pointer to the port struct.
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|
* @param[in] portNum The port number.
|
|
*/
|
|
void TMIO_initPort(TmioPort *const port, const u8 portNum);
|
|
|
|
/**
|
|
* @brief Checks if a MMC/SD card is inserted.
|
|
*
|
|
* @return Returns true if a card is inserted.
|
|
*/
|
|
bool TMIO_cardDetected(void);
|
|
|
|
/**
|
|
* @brief Checks if the write protect slider is set to locked.
|
|
*
|
|
* @return Returns true if the card is unlocked.
|
|
*/
|
|
bool TMIO_cardWritable(void);
|
|
|
|
/**
|
|
* @brief Handles the device specific powerup sequence including the 74 clocks.
|
|
*
|
|
* @param port A pointer to the port struct.
|
|
*/
|
|
void TMIO_powerupSequence(TmioPort *const port);
|
|
|
|
/**
|
|
* @brief Sends a command.
|
|
*
|
|
* @param port A pointer to the port struct.
|
|
* @param[in] cmd The command.
|
|
* @param[in] arg The argument for the command.
|
|
*
|
|
* @return Returns 0 on success otherwise see REG_SD_STATUS1/2 bits.
|
|
*/
|
|
u32 TMIO_sendCommand(TmioPort *const port, const u16 cmd, const u32 arg);
|
|
|
|
/**
|
|
* @brief Sets the clock for a tmio port.
|
|
*
|
|
* @param port A pointer to the port struct.
|
|
* @param[in] clk The target clock in Hz.
|
|
*/
|
|
ALWAYS_INLINE void TMIO_setClock(TmioPort *const port, const u32 clk)
|
|
{
|
|
port->sd_clk_ctrl = SD_CLK_PWR_SAVE | SD_CLK_EN | TMIO_clk2div(clk)>>2;
|
|
}
|
|
|
|
/**
|
|
* @brief Sets the transfer block length for a tmio port.
|
|
*
|
|
* @param port A pointer to the port struct.
|
|
* @param[in] blockLen The block length. Caution: Provide a buffer with multiple of 4 size regardless of block length.
|
|
*/
|
|
ALWAYS_INLINE void TMIO_setBlockLen(TmioPort *const port, u16 blockLen)
|
|
{
|
|
if(blockLen > 512) blockLen = 512;
|
|
|
|
port->sd_blocklen = blockLen;
|
|
}
|
|
|
|
/**
|
|
* @brief Sets the bus width for a tmio port.
|
|
*
|
|
* @param port A pointer to the port struct.
|
|
* @param[in] width The bus width.
|
|
*/
|
|
ALWAYS_INLINE void TMIO_setBusWidth(TmioPort *const port, const u8 width)
|
|
{
|
|
port->sd_option = (width == 4 ? OPTION_BUS_WIDTH4 : OPTION_BUS_WIDTH1) |
|
|
OPTION_UNK14 | OPTION_DEFAULT_TIMINGS;
|
|
}
|
|
|
|
/**
|
|
* @brief Sets a transfer buffer for a tmio port.
|
|
*
|
|
* @param port A pointer to the port struct.
|
|
* @param buf The buffer pointer.
|
|
* @param[in] blocks The number of blocks to transfer.
|
|
*/
|
|
ALWAYS_INLINE void TMIO_setBuffer(TmioPort *const port, void *buf, const u16 blocks)
|
|
{
|
|
port->buf = buf;
|
|
port->blocks = blocks;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
} // extern "C"
|
|
#endif |