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https://gitee.com/anod/open_agb_firm.git
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78da297199
gfx: 常量大改名、函数大改名，增加了双缓冲的一些驱动函数 其他：基本是ARM9/ARM11宏修改和BIT取值修改，bool从c风格转成c++强类型风格等。sha.c使用了memory.h进行的改动(copy32)
97 lines
3.1 KiB
C
97 lines
3.1 KiB
C
#pragma once
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/*
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* This file is part of open_agb_firm
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* Copyright (C) 2021 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifdef __ARM9__
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#include "arm9/drivers/interrupt.h"
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#include "arm9/drivers/cfg9.h"
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#elif __ARM11__
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#include "arm11/drivers/interrupt.h"
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#endif // #ifdef __ARM9__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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// Note on port numbers:
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// To make things easier 2 ports are assigned to each controller.
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// There are a maximum of 2 controllers mapped at the same time
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// and 3 (on DSi 2) controllers in total.
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// Also see tmio.h.
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//
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// Examples:
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// Port 0 is port 0 on controller 1, port 3 is port 1 on controller 2.
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// This define determines whenever the SD slot is accessible on
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// ARM9 or ARM11 when TMIO_CARD_PORT for ARM9 is set to 2.
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#define TMIO_C2_MAP (0u) // Controller 2 (physical 3) memory mapping. 0=ARM9 0x10007000 or 1=ARM11 0x10100000.
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#ifdef __ARM9__
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#define TMIO_CARD_PORT (2u) // Can be on port 0 or 2. 0 always on ARM9.
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#define TMIO_eMMC_PORT (1u) // Port 1 only. Do not change.
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#elif __ARM11__
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#define TMIO_CARD_PORT (2u) // Port 2 only. Do not change.
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#define TMIO_eMMC_PORT (3u) // Placeholder. Do not change. Not connected/accessible.
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#endif // #ifdef __ARM9__
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// Don't modify anything below!
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#ifdef __ARM9__
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#define TMIO_MAP_CONTROLLERS() \
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{ \
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getCfg9Regs()->sdmmcctl = (TMIO_CARD_PORT == 2u ? SDMMCCTL_CARD_TMIO3_SEL : SDMMCCTL_CARD_TMIO1_SEL) | \
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(TMIO_C2_MAP == 1u ? SDMMCCTL_TMIO3_MAP11 : SDMMCCTL_TMIO3_MAP9) | \
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SDMMCCTL_UNK_BIT6 | SDMMCCTL_UNK_PWR_OFF; \
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}
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#define TMIO_UNMAP_CONTROLLERS() {getCfg9Regs()->sdmmcctl = SDMMCCTL_UNK_BIT6 | SDMMCCTL_UNK_PWR_OFF | SDMMCCTL_CARD_PWR_OFF;}
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#define TMIO_NUM_CONTROLLERS (TMIO_C2_MAP == 0u ? 2u : 1u)
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#define TMIO_IRQ_ID_CONTROLLER1 (IRQ_TMIO1)
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#define TMIO_REGISTER_ISR(isr) \
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{ \
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IRQ_registerIsr(IRQ_TMIO1, (isr)); \
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if(TMIO_NUM_CONTROLLERS == 2u) \
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IRQ_registerIsr(IRQ_TMIO3, (isr)); \
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}
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#elif __ARM11__
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#define TMIO_MAP_CONTROLLERS()
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#define TMIO_UNMAP_CONTROLLERS()
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#define TMIO_NUM_CONTROLLERS (TMIO_C2_MAP == 1u ? 2u : 1u)
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#define TMIO_IRQ_ID_CONTROLLER1 (IRQ_TMIO2)
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#define TMIO_REGISTER_ISR(isr) \
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{ \
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IRQ_registerIsr(IRQ_TMIO2, 14, 0, (isr)); \
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if(TMIO_NUM_CONTROLLERS == 2u) \
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IRQ_registerIsr(IRQ_TMIO3, 14, 0, (isr)); \
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}
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#endif // #ifdef __ARM9__
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#define TMIO_UNREGISTER_ISR() \
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{ \
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IRQ_unregisterIsr(TMIO_IRQ_ID_CONTROLLER1); \
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if(TMIO_NUM_CONTROLLERS == 2u) \
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IRQ_unregisterIsr(IRQ_TMIO3); \
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}
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#ifdef __cplusplus
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} // extern "C"
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#endif |