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c04e09a770
type.h: 针对c++使用了c++23的using语法定义typedef memory.h/memory.c 提供了不对齐拷贝32位值的实现 其他大部分头文件，只是提供了c++的头文件支持
135 lines
4.9 KiB
C
135 lines
4.9 KiB
C
#pragma once
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/*
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* This file is part of open_agb_firm
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* Copyright (C) 2023 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifdef __ARM9__
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// ITCM.
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#define ITCM_BASE (0x00000000)
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#define ITCM_KERN9_MIRROR (0x01FF8000)
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#define ITCM_BOOT9_MIRROR (0x07FF8000)
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#define ITCM_SIZE (0x00008000) // 32 KiB.
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// AHB RAM (ARM9 memory).
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#define AHB_RAM_BASE (0x08000000)
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#define AHB_RAM_EXT_BASE (AHB_RAM_BASE + AHB_RAM_SIZE)
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#define AHB_RAM_SIZE (0x00100000) // 1 MiB.
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#define AHB_RAM_EXT_SIZE (0x00080000) // 512 KiB.
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// AHB memory mapped IO registers.
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#define IO_AHB_BASE (0x10000000)
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#define IO_AHB_SIZE (0x00100000) // 1 MiB.
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// DTCM.
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#define DTCM_BASE (0xFFF00000)
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#define DTCM_SIZE (0x00004000) // 16 KiB.
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// ARM9 bootrom.
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#define BOOT9_BASE (0xFFFF0000)
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#define BOOT9_SIZE (0x00010000) // 64 KiB.
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#endif // #ifdef __ARM9__
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#ifdef __ARM11__
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// ARM11 bootrom.
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#define BOOT11_BASE (0x00000000)
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#define BOOT11_LO_MIRROR (0x00010000)
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#define BOOT11_HI_MIRROR (0xFFFF0000)
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#define BOOT11_SIZE (0x00010000) // 64 KiB.
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// AXI memory mapped IO registers.
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#define IO_AXI_BASE (0x10200000)
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#define IO_AXI_SIZE (0x00300000) // 3 MiB (guess).
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// ARM11 MPCore private memory region.
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#define MPCORE_PRIV_BASE (0x17E00000)
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#define MPCORE_PRIV_SIZE (0x00002000) // 8 KiB.
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// L2C-310 Level 2 Cache Controller.
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#define L2C_BASE (0x17E10000)
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#define L2C_SIZE (0x00001000) // 4 KiB.
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// QTM RAM.
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#define QTM_RAM_BASE (0x1F000000)
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#define QTM_RAM_SIZE (0x00400000) // 4 MiB.
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#endif // #ifdef __ARM11__
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// Common memory mapped IO registers.
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#define IO_COMMON_BASE (0x10100000)
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#define IO_COMMON_SIZE (0x00100000) // 1 MiB.
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// VRAM.
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#define VRAM_BASE (0x18000000)
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#define VRAM_BANK0 (VRAM_BASE)
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#define VRAM_BANK1 (VRAM_BASE + VRAM_SIZE / 2)
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#define VRAM_SIZE (0x00600000) // 6 MiB.
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#define VRAM_BANK_SIZE (VRAM_SIZE / 2)
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// DSP RAM (DSP memory).
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#define DSP_RAM_BASE (0x1FF00000)
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#define DSP_RAM_SIZE (0x00080000) // 512 KiB.
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// AXI RAM (AXIWRAM).
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#define AXI_RAM_BASE (0x1FF80000)
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#define AXI_RAM_SIZE (0x00080000) // 512 KiB.
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// FCRAM.
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#define FCRAM_BASE (0x20000000)
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#define FCRAM_EXT_BASE (FCRAM_BASE + FCRAM_SIZE)
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#define FCRAM_SIZE (0x08000000) // 128 MiB.
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#define FCRAM_EXT_SIZE (FCRAM_SIZE)
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// Custom mappings.
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#ifdef __ARM9__
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#define A9_VECTORS_START (AHB_RAM_BASE)
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#define A9_VECTORS_SIZE (0x40)
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#define A9_STUB_ENTRY (ITCM_KERN9_MIRROR + ITCM_SIZE - 0x200)
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#define A9_STUB_SIZE (0x200)
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#define A9_HEAP_END (AHB_RAM_BASE + AHB_RAM_SIZE)
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#define A9_STACK_START (DTCM_BASE)
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#define A9_STACK_END (DTCM_BASE + DTCM_SIZE - 0x400)
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#define A9_IRQ_STACK_START (DTCM_BASE + DTCM_SIZE - 0x400)
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#define A9_IRQ_STACK_END (DTCM_BASE + DTCM_SIZE)
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#define A9_EXC_STACK_START (ITCM_KERN9_MIRROR + (ITCM_SIZE / 2))
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#define A9_EXC_STACK_END (ITCM_KERN9_MIRROR + ITCM_SIZE)
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#define FIRM_LOAD_ADDR (VRAM_BASE + 0x200000)
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#define RAM_FIRM_BOOT_ADDR (FCRAM_BASE + 0x1000)
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#endif // #ifdef __ARM9__
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#ifdef __ARM11__
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#define A11_C0_STACK_START (AXI_RAM_BASE) // Core 0 stack.
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#define A11_C0_STACK_END (A11_C0_STACK_START + 0x2000)
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#define A11_C1_STACK_START (A11_C0_STACK_END) // Core 1 stack.
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#define A11_C1_STACK_END (A11_C1_STACK_START + 0x2000)
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// WARNING: The stacks for core 2/3 are temporary.
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#define A11_C2_STACK_START (FCRAM_BASE - 0x600) // Core 2 stack.
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#define A11_C2_STACK_END (FCRAM_BASE - 0x400)
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#define A11_C3_STACK_START (FCRAM_BASE - 0x400) // Core 3 stack.
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#define A11_C3_STACK_END (FCRAM_BASE - 0x200)
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#define A11_EXC_STACK_START (VRAM_BASE + VRAM_SIZE - 0x200000)
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#define A11_EXC_STACK_END (VRAM_BASE + VRAM_SIZE - 0x100000)
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#define A11_MMU_TABLES_BASE (A11_C1_STACK_END)
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#define A11_VECTORS_START (AXI_RAM_BASE + AXI_RAM_SIZE - 0x60)
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#define A11_VECTORS_SIZE (0x60)
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#define A11_FALLBACK_ENTRY (AXI_RAM_BASE + AXI_RAM_SIZE - 0x4)
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#define A11_STUB_ENTRY (AXI_RAM_BASE + AXI_RAM_SIZE - 0x200)
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#define A11_STUB_SIZE (0x1A0) // Don't overwrite the vectors.
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#define A11_HEAP_END (AXI_RAM_BASE + AXI_RAM_SIZE)
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#endif // #ifdef __ARM11__
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