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132 lines
3.6 KiB
ArmAsm
132 lines
3.6 KiB
ArmAsm
/*
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* This file is part of open_agb_firm
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* Copyright (C) 2021 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "asm_macros.h"
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.syntax unified
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.cpu mpcore
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.fpu vfpv2
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#define ICACHE_SIZE (0x4000)
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#define DCACHE_SIZE (0x4000)
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#define CACHE_LINE_SIZE (32)
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BEGIN_ASM_FUNC invalidateICache
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate Entire Instruction Cache, also flushes the branch target cache
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@mcr p15, 0, r0, c7, c5, 6 @ Flush Entire Branch Target Cache
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mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
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mcr p15, 0, r0, c7, c5, 4 @ Flush Prefetch Buffer
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC invalidateICacheRange
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add r1, r1, r0
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bic r0, r0, #(CACHE_LINE_SIZE - 1)
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mov r2, #0
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invalidateICacheRange_lp:
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mcr p15, 0, r0, c7, c5, 1 @ Invalidate Instruction Cache Line (using MVA)
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add r0, r0, #CACHE_LINE_SIZE
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cmp r0, r1
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blt invalidateICacheRange_lp
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mcr p15, 0, r2, c7, c5, 6 @ Flush Entire Branch Target Cache
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mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier
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mcr p15, 0, r2, c7, c5, 4 @ Flush Prefetch Buffer
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC cleanDCache
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 0 @ Clean Entire Data Cache
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mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC flushDCache
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mov r0, #0
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mcr p15, 0, r0, c7, c14, 0 @ Clean and Invalidate Entire Data Cache
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mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC cleanDCacheRange
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cmp r1, #DCACHE_SIZE
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bhi cleanDCache
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add r1, r1, r0
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bic r0, r0, #(CACHE_LINE_SIZE - 1)
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mov r2, #0
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cleanDCacheRange_lp:
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mcr p15, 0, r0, c7, c10, 1 @ Clean Data Cache Line (using MVA)
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add r0, r0, #CACHE_LINE_SIZE
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cmp r0, r1
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blt cleanDCacheRange_lp
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mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC flushDCacheRange
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cmp r1, #DCACHE_SIZE
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bhi flushDCache
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add r1, r1, r0
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bic r0, r0, #(CACHE_LINE_SIZE - 1)
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mov r2, #0
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flushDCacheRange_lp:
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mcr p15, 0, r0, c7, c14, 1 @ Clean and Invalidate Data Cache Line (using MVA)
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add r0, r0, #CACHE_LINE_SIZE
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cmp r0, r1
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blt flushDCacheRange_lp
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mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC invalidateDCache
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mov r0, #0
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mcr p15, 0, r0, c7, c6, 0 @ Invalidate Entire Data Cache
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mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC invalidateDCacheRange
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cmp r1, #DCACHE_SIZE
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bhi flushDCache
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add r1, r1, r0
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tst r0, #(CACHE_LINE_SIZE - 1)
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mcrne p15, 0, r0, c7, c10, 1 @ Clean Data Cache Line (using MVA)
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tst r1, #(CACHE_LINE_SIZE - 1)
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mcrne p15, 0, r1, c7, c10, 1 @ Clean Data Cache Line (using MVA)
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bic r0, r0, #(CACHE_LINE_SIZE - 1)
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mov r2, #0
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invalidateDCacheRange_lp:
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mcr p15, 0, r0, c7, c6, 1 @ Invalidate Data Cache Line (using MVA)
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add r0, r0, #CACHE_LINE_SIZE
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cmp r0, r1
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blt invalidateDCacheRange_lp
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mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier
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bx lr
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END_ASM_FUNC
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