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https://gitee.com/anod/open_agb_firm.git
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536 lines
16 KiB
C
536 lines
16 KiB
C
/*
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* This file is part of open_agb_firm
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* Copyright (C) 2021 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <stdatomic.h>
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#include "types.h"
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#include "fb_assert.h"
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#include "drivers/gfx.h"
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#include "arm11/drivers/cfg11.h"
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#include "arm11/drivers/pdn.h"
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#include "arm11/drivers/lcd.h"
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#include "arm11/drivers/gx.h"
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#include "arm11/drivers/gpu_regs.h"
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#include "mem_map.h"
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#include "mmio.h"
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#include "arm11/drivers/i2c.h"
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#include "arm11/drivers/mcu.h"
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#include "arm11/debug.h"
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#include "arm11/drivers/interrupt.h"
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#include "arm11/drivers/timer.h"
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#include "arm.h"
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#include "util.h"
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#include "arm11/allocator/vram.h"
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#include "kevent.h"
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#define MCU_LCD_IRQ_MASK (MCU_IRQ_TOP_BL_ON | MCU_IRQ_TOP_BL_OFF | \
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MCU_IRQ_BOT_BL_ON | MCU_IRQ_BOT_BL_OFF | \
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MCU_IRQ_LCD_POWER_ON | MCU_IRQ_LCD_POWER_OFF)
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static struct
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{
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u32 swap; // Currently active framebuffer.
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void *framebufs[2][4]; // For each screen A1, A2, B1, B2
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KHandle events[6];
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u8 doubleBuf[2]; // Top, bottom, 1 = enable.
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u8 lcdPower; // 1 = on. Bit 4 top light, bit 2 bottom light, bit 0 LCDs.
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u16 lcdLights[2]; // LCD backlight brightness. Top, bottom.
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u32 formats[2]; // Top, bottom
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u16 strides[2]; // Top, bottom
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} g_gfxState = {0};
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static u8 fmt2PixSize(GfxFbFmt fmt);
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static void setupFramebufs(GfxFbFmt fmtTop, GfxFbFmt fmtBot);
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static void deallocFramebufs(void);
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static void setupDislayController(u8 lcd);
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void GFX_init(GfxFbFmt fmtTop, GfxFbFmt fmtBot)
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{
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g_gfxState.lcdPower = 0x15; // All on.
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setupFramebufs(fmtTop, fmtBot);
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g_gfxState.doubleBuf[0] = 1;
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g_gfxState.doubleBuf[1] = 1;
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// FIXME: Temporary workaround for screen init compatibility (Luma/fb3DS 1.2).
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TIMER_sleepMs(50);
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(void)MCU_getIrqs(MCU_LCD_IRQ_MASK); // Discard any screen init events.
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getCfg11Regs()->gpuprot = GPUPROT_NO_PROT;
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// Reset the whole GX block.
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Pdn *const pdn = getPdnRegs();
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pdn->gpu_cnt = PDN_GPU_CNT_CLK_EN;
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wait_cycles(12);
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pdn->gpu_cnt = PDN_GPU_CNT_CLK_EN | PDN_GPU_CNT_NORST_ALL;
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REG_GX_GPU_CLK = 0x100; // P3D
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REG_GX_PSC_VRAM = 0; // All VRAM banks enabled.
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// These 3 reg writes are normally done way later in the
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// init but we will be fine doing it early.
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REG_GX_PSC_FILL0_CNT = 0;
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REG_GX_PSC_FILL1_CNT = 0;
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REG_GX_PPF_CNT = 0;
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// PDC/framebuffer setup. This must be done before LCD init.
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setupDislayController(0);
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setupDislayController(1);
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REG_LCD_PDC0_SWAP = 0; // Select framebuf 0.
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REG_LCD_PDC1_SWAP = 0; // Select framebuf 0.
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REG_LCD_PDC0_CNT = PDC_CNT_OUT_E | PDC_CNT_I_MASK_ERR | PDC_CNT_I_MASK_H | PDC_CNT_E; // Start
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REG_LCD_PDC1_CNT = PDC_CNT_OUT_E | PDC_CNT_I_MASK_ALL | PDC_CNT_E; // Start
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// LCD reg setup.
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REG_LCD_ABL0_FILL = 1u<<24; // Force blackscreen.
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REG_LCD_ABL1_FILL = 1u<<24; // Force blackscreen.
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REG_LCD_PARALLAX_CNT = 0;
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REG_LCD_PARALLAX_PWM = 0xA390A39;
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REG_LCD_RST = 0; // Reset LCD drivers. Unknown for how long this must be low.
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// GSP seems to rely on boot11/previous FIRM having set it to 0 already.
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REG_LCD_UNK00C = 0x10001; // Stops H-/V-sync control signals?
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// Create IRQ events.
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// PSC0, PSC1, PDC0, PDC1, PPF, P3D
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for(u8 i = 0; i < 6; i++)
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{
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KHandle tmp = createEvent(false);
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bindInterruptToEvent(tmp, IRQ_PSC0 + i, 14);
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g_gfxState.events[i] = tmp;
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}
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// Clear entire VRAM.
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GX_memoryFill((u32*)VRAM_BANK0, 1u<<9, VRAM_SIZE / 2, 0,
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(u32*)VRAM_BANK1, 1u<<9, VRAM_SIZE / 2, 0);
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// Backlight and other stuff.
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REG_LCD_ABL0_LIGHT = 0;
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REG_LCD_ABL0_CNT = 0;
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REG_LCD_ABL0_LIGHT_PWM = 0;
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REG_LCD_ABL1_LIGHT = 0;
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REG_LCD_ABL1_CNT = 0;
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REG_LCD_ABL1_LIGHT_PWM = 0;
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// Timing critical part start.
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// This must be done within 4 frames.
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REG_LCD_RST = 1; // Take LCD drivers out of reset.
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// At this point the output must be forced black or
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// the LCD drivers will not sync. Already done above.
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REG_LCD_UNK00C = 0; // Starts H-/V-sync control signals?
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TIMER_sleepMs(10); // Wait for power supply (which?) to stabilize and LCD drivers to finish resetting.
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LCDI2C_init(); // Initialize LCD drivers.
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MCU_setLcdPower(2u); // Power on LCDs (MCU --> PMIC).
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// Timing critical part end.
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// Wait 50 us for LCD sync. The MCU event wait will cover this.
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if(MCU_waitIrqs(MCU_LCD_IRQ_MASK) != MCU_IRQ_LCD_POWER_ON) panic();
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// The transfer engine is (sometimes) borked on screen init.
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// Doing a dummy texture copy fixes it.
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// TODO: Proper fix.
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//GX_textureCopy((u32*)RENDERBUF_TOP, 0, (u32*)RENDERBUF_BOT, 0, 16);
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LCDI2C_waitBacklightsOn();
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REG_LCD_ABL0_LIGHT_PWM = 0x1023E; // TODO: Figure out how this works.
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REG_LCD_ABL0_LIGHT = 1;
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REG_LCD_ABL1_LIGHT_PWM = 0x1023E; // TODO: Figure out how this works.
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REG_LCD_ABL1_LIGHT = 1;
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MCU_setLcdPower(0x28u); // Power on backlights.
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if(MCU_waitIrqs(MCU_LCD_IRQ_MASK) != (MCU_IRQ_TOP_BL_ON | MCU_IRQ_BOT_BL_ON)) panic();
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// Make sure the fills finished.
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GFX_waitForPSC0();
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GFX_waitForPSC1();
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REG_LCD_ABL0_FILL = 0;
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REG_LCD_ABL1_FILL = 0;
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// GPU stuff.
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REG_GX_GPU_CLK = 0x70100;
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*((vu32*)0x10400050) = 0x22221200;
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*((vu32*)0x10400054) = 0xFF2;
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REG_GX_P3D(GPUREG_IRQ_ACK) = 0;
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REG_GX_P3D(GPUREG_IRQ_CMP) = 0x12345678;
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REG_GX_P3D(GPUREG_IRQ_MASK) = 0xFFFFFFF0;
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REG_GX_P3D(GPUREG_IRQ_AUTOSTOP) = 1;
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// This reg needs to be set to 1 (configuration)
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// before running the first cmd list.
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REG_GX_P3D(GPUREG_START_DRAW_FUNC0) = 1;
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}
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void GFX_deinit(void)
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{
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// Power off backlights if on.
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const u8 power = g_gfxState.lcdPower;
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if(power & ~1u)
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{
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MCU_setLcdPower(power & ~1u);
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if(MCU_waitIrqs(MCU_LCD_IRQ_MASK) != (u32)(power & ~1u)<<24) panic();
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}
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GFX_setBrightness(0, 0);
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REG_LCD_ABL0_LIGHT_PWM = 0;
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REG_LCD_ABL1_LIGHT_PWM = 0;
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// Make sure the LCDs are completely black.
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REG_LCD_ABL0_FILL = 1u<<24; // Force blackscreen.
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REG_LCD_ABL1_FILL = 1u<<24; // Force blackscreen.
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GFX_waitForVBlank0();
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GFX_waitForVBlank0();
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// Reset the LCD drivers.
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// And stop the H-/V-sync control signals?
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REG_LCD_RST = 0;
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REG_LCD_UNK00C = 0x10001;
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// Power off LCDs if on.
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if(power & 1u)
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{
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MCU_setLcdPower(1u);
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if(MCU_waitIrqs(MCU_LCD_IRQ_MASK) != MCU_IRQ_LCD_POWER_OFF) panic();
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}
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// TODO: Wait until PDC is not reading any data from mem.
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REG_LCD_PDC0_CNT = PDC_CNT_I_MASK_ALL; // Stop
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REG_LCD_PDC0_SWAP = PDC_SWAP_RST_FIFO | PDC_SWAP_I_ALL; // Reset FIFO and clear IRQs.
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REG_LCD_PDC1_CNT = PDC_CNT_I_MASK_ALL; // Start
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REG_LCD_PDC1_SWAP = PDC_SWAP_RST_FIFO | PDC_SWAP_I_ALL; // Reset FIFO and clear IRQs.
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REG_GX_PSC_VRAM = 0xF00;
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REG_GX_GPU_CLK = 0;
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getPdnRegs()->gpu_cnt = PDN_GPU_CNT_CLK_EN | PDN_GPU_CNT_NORST_REGS;
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deallocFramebufs();
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// PSC0, PSC1, PDC0, PDC1, PPF, P3D
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for(u8 i = 0; i < 6; i++)
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{
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unbindInterruptEvent(IRQ_PSC0 + i);
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deleteEvent(g_gfxState.events[i]);
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g_gfxState.events[i] = 0;
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}
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}
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void GFX_setFramebufFmt(GfxFbFmt fmtTop, GfxFbFmt fmtBot)
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{
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REG_LCD_ABL0_FILL = 1u<<24; // Force blackscreen
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REG_LCD_ABL1_FILL = 1u<<24; // Force blackscreen
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if(fmtTop < (g_gfxState.formats[0] & 7u) || fmtBot < (g_gfxState.formats[1] & 7u))
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{
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deallocFramebufs();
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setupFramebufs(fmtTop, fmtBot);
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}
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// Update PDC regs.
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REG_LCD_PDC0_FB_A1 = (u32)g_gfxState.framebufs[0][0];
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REG_LCD_PDC0_FB_A2 = (u32)g_gfxState.framebufs[0][1];
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REG_LCD_PDC0_FB_B1 = (u32)g_gfxState.framebufs[0][2];
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REG_LCD_PDC0_FB_B2 = (u32)g_gfxState.framebufs[0][3];
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REG_LCD_PDC0_STRIDE = g_gfxState.strides[0];
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REG_LCD_PDC0_FMT = g_gfxState.formats[0];
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REG_LCD_PDC1_FB_A1 = (u32)g_gfxState.framebufs[1][0];
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REG_LCD_PDC1_FB_A2 = (u32)g_gfxState.framebufs[1][1];
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REG_LCD_PDC1_FB_B1 = (u32)g_gfxState.framebufs[1][2];
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REG_LCD_PDC1_FB_B2 = (u32)g_gfxState.framebufs[1][3];
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REG_LCD_PDC1_STRIDE = g_gfxState.strides[1];
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REG_LCD_PDC1_FMT = g_gfxState.formats[1];
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REG_LCD_ABL0_FILL = 0;
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REG_LCD_ABL1_FILL = 0;
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}
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static u8 fmt2PixSize(GfxFbFmt fmt)
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{
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u8 size;
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switch(fmt)
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{
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case GFX_RGBA8:
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size = 4;
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break;
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case GFX_BGR8:
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size = 3;
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break;
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default: // 2 = RGB565, 3 = RGB5A1, 4 = RGBA4
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size = 2;
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}
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return size;
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}
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static void setupFramebufs(GfxFbFmt fmtTop, GfxFbFmt fmtBot)
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{
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const u8 topPixSize = fmt2PixSize(fmtTop);
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const u8 botPixSize = fmt2PixSize(fmtBot);
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g_gfxState.strides[0] = 240u * topPixSize; // No gap.
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g_gfxState.strides[1] = 240u * botPixSize; // No gap.
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const u32 topSize = 400u * 240 * topPixSize;
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const u32 botSize = 320u * 240 * botPixSize;
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g_gfxState.framebufs[0][0] = vramAlloc(topSize); // Top A1 (3D left eye)
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void *botPtr = vramAlloc(botSize);
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g_gfxState.framebufs[1][0] = botPtr; // Bottom A1
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g_gfxState.framebufs[1][2] = botPtr; // Bottom B1 (unused)
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g_gfxState.framebufs[0][2] = vramAlloc(topSize); // Top B1 (3D right eye)
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g_gfxState.framebufs[0][1] = vramAlloc(topSize); // Top A2 (3D left eye)
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botPtr = vramAlloc(botSize);
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g_gfxState.framebufs[1][1] = botPtr; // Bottom A2
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g_gfxState.framebufs[1][3] = botPtr; // Bottom B2 (unused)
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g_gfxState.framebufs[0][3] = vramAlloc(topSize); // Top B2 (3D right eye)
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g_gfxState.formats[0] = 0u<<16 | 3u<<8 | 1u<<6 | 0u<<4 | fmtTop;
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g_gfxState.formats[1] = 0u<<16 | 3u<<8 | 0u<<6 | 0u<<4 | fmtBot;
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}
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static void deallocFramebufs(void)
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{
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vramFree(g_gfxState.framebufs[0][3]);
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vramFree(g_gfxState.framebufs[1][1]);
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vramFree(g_gfxState.framebufs[0][1]);
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vramFree(g_gfxState.framebufs[0][2]);
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vramFree(g_gfxState.framebufs[1][0]);
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vramFree(g_gfxState.framebufs[0][0]);
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}
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static void setupDislayController(u8 lcd)
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{
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if(lcd > 1) return;
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static const u32 displayCfgs[2][24] =
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{
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{
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// PDC0 regs 0-0x4C.
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450, 209, 449, 449, 0, 207, 209, 453<<16 | 449,
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1<<16 | 0, 413, 2, 402, 402, 402, 1, 2,
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406<<16 | 402, 0, 0<<4 | 0, 0<<16 | 0xFF<<8 | 0,
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// PDC0 regs 0x5C-0x64.
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400<<16 | 240, // Width and height.
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449<<16 | 209,
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402<<16 | 2,
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// PDC0 reg 0x9C.
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0<<16 | 0
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},
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{
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// PDC1 regs 0-0x4C.
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450, 209, 449, 449, 205, 207, 209, 453<<16 | 449,
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1<<16 | 0, 413, 82, 402, 402, 79, 80, 82,
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408<<16 | 404, 0, 1<<4 | 1, 0<<16 | 0<<8 | 0xFF,
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// PDC1 regs 0x5C-0x64.
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320<<16 | 240, // Width and height.
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449<<16 | 209,
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402<<16 | 82,
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// PDC1 reg 0x9C.
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0<<16 | 0
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}
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};
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const u32 *const cfg = displayCfgs[lcd];
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vu32 *const regs = (vu32*)(GX_REGS_BASE + 0x400 + (0x100u * lcd));
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iomemcpy(regs, cfg, 0x50); // PDC regs 0-0x4C.
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iomemcpy(regs + 23, &cfg[20], 0xC); // PDC regs 0x5C-0x64.
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regs[36] = g_gfxState.strides[lcd]; // PDC reg 0x90 stride.
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regs[39] = cfg[23]; // PDC reg 0x9C.
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// PDC regs 0x68, 0x6C, 0x94, 0x98 and 0x70.
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regs[26] = (u32)g_gfxState.framebufs[lcd][0]; // Framebuffer A first address.
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regs[27] = (u32)g_gfxState.framebufs[lcd][1]; // Framebuffer A second address.
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regs[37] = (u32)g_gfxState.framebufs[lcd][2]; // Framebuffer B first address.
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regs[38] = (u32)g_gfxState.framebufs[lcd][3]; // Framebuffer B second address.
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regs[28] = g_gfxState.formats[lcd]; // Format
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regs[32] = 0; // Gamma table index 0.
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for(u32 i = 0; i < 256; i++) regs[33] = 0x10101u * i;
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}
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void GFX_powerOnBacklights(GfxBlight mask)
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{
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fb_assert((mask & ~GFX_BLIGHT_BOTH) == 0u);
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g_gfxState.lcdPower |= mask;
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mask <<= 1;
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MCU_setLcdPower(mask); // Power on backlights.
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if(MCU_waitIrqs(MCU_LCD_IRQ_MASK) != (u32)mask<<24) panic();
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}
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void GFX_powerOffBacklights(GfxBlight mask)
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{
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fb_assert((mask & ~GFX_BLIGHT_BOTH) == 0u);
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g_gfxState.lcdPower &= ~mask;
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MCU_setLcdPower(mask); // Power off backlights.
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if(MCU_waitIrqs(MCU_LCD_IRQ_MASK) != (u32)mask<<24) panic();
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}
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void GFX_setBrightness(u16 top, u16 bot)
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{
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top &= 0x3ff;
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bot &= 0x3ff;
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g_gfxState.lcdLights[0] = top;
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g_gfxState.lcdLights[1] = bot;
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REG_LCD_ABL0_LIGHT = top;
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REG_LCD_ABL1_LIGHT = bot;
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}
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void GFX_setForceBlack(bool top, bool bot)
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{
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REG_LCD_ABL0_FILL = (u32)top<<24; // Force blackscreen
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REG_LCD_ABL1_FILL = (u32)bot<<24; // Force blackscreen
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}
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void GFX_setDoubleBuffering(u8 screen, bool dBuf)
|
|
{
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g_gfxState.doubleBuf[screen] = dBuf;
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|
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if(!dBuf)
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{
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if(screen == SCREEN_TOP) REG_LCD_PDC0_SWAP = 0;
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else REG_LCD_PDC1_SWAP = 0;
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}
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}
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|
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void* GFX_getFramebuffer(u8 screen)
|
|
{
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const u32 idx = (g_gfxState.swap ^ 1u) & g_gfxState.doubleBuf[screen];
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return g_gfxState.framebufs[screen][idx];
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}
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|
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void GFX_swapFramebufs(void)
|
|
{
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u32 swap = g_gfxState.swap;
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swap ^= 1u;
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g_gfxState.swap = swap;
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|
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swap |= PDC_SWAP_I_ALL; // Acknowledge IRQs.
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if(g_gfxState.doubleBuf[0]) REG_LCD_PDC0_SWAP = swap;
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if(g_gfxState.doubleBuf[1]) REG_LCD_PDC1_SWAP = swap;
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}
|
|
|
|
void GFX_waitForEvent(GfxEvent event, bool discard)
|
|
{
|
|
KHandle kevent = g_gfxState.events[event];
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|
|
|
if(discard) clearEvent(kevent);
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|
waitForEvent(kevent);
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|
clearEvent(kevent);
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|
}
|
|
|
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void GX_memoryFill(u32 *buf0a, u32 buf0v, u32 buf0Sz, u32 val0, u32 *buf1a, u32 buf1v, u32 buf1Sz, u32 val1)
|
|
{
|
|
if(buf0a)
|
|
{
|
|
REG_GX_PSC_FILL0_S_ADDR = (u32)buf0a>>3;
|
|
REG_GX_PSC_FILL0_E_ADDR = ((u32)buf0a + buf0Sz)>>3;
|
|
REG_GX_PSC_FILL0_VAL = val0;
|
|
REG_GX_PSC_FILL0_CNT = buf0v | 1u; // Pattern + start
|
|
}
|
|
|
|
if(buf1a)
|
|
{
|
|
REG_GX_PSC_FILL1_S_ADDR = (u32)buf1a>>3;
|
|
REG_GX_PSC_FILL1_E_ADDR = ((u32)buf1a + buf1Sz)>>3;
|
|
REG_GX_PSC_FILL1_VAL = val1;
|
|
REG_GX_PSC_FILL1_CNT = buf1v | 1u; // Pattern + start
|
|
}
|
|
}
|
|
|
|
// Example: GX_displayTransfer(in, 160u<<16 | 240u, out, 160u<<16 | 240u, 2u<<12 | 2u<<8);
|
|
// Copy and unswizzle GBA sized frame in RGB565.
|
|
void GX_displayTransfer(const u32 *const in, u32 indim, u32 *out, u32 outdim, u32 flags)
|
|
{
|
|
if(!in || !out) return;
|
|
|
|
REG_GX_PPF_IN_ADDR = (u32)in>>3;
|
|
REG_GX_PPF_OUT_ADDR = (u32)out>>3;
|
|
REG_GX_PPF_DT_INDIM = indim;
|
|
REG_GX_PPF_DT_OUTDIM = outdim;
|
|
REG_GX_PPF_FlAGS = flags;
|
|
REG_GX_PPF_UNK14 = 0;
|
|
REG_GX_PPF_CNT = 1;
|
|
}
|
|
|
|
// Example: GX_textureCopy(in, (240 * 2)<<12 | (240 * 2)>>4, out, (240 * 2)<<12 | (240 * 2)>>4, 240 * 400);
|
|
// Copies every second line of a 240x400 framebuffer.
|
|
void GX_textureCopy(const u32 *const in, u32 indim, u32 *out, u32 outdim, u32 size)
|
|
{
|
|
if(!in || !out) return;
|
|
|
|
REG_GX_PPF_IN_ADDR = (u32)in>>3;
|
|
REG_GX_PPF_OUT_ADDR = (u32)out>>3;
|
|
REG_GX_PPF_FlAGS = 1u<<3;
|
|
REG_GX_PPF_LEN = size;
|
|
REG_GX_PPF_TC_INDIM = indim;
|
|
REG_GX_PPF_TC_OUTDIM = outdim;
|
|
REG_GX_PPF_CNT = 1;
|
|
}
|
|
|
|
void GX_processCommandList(u32 size, const u32 *const cmdList)
|
|
{
|
|
REG_GX_P3D(GPUREG_IRQ_ACK) = 0; // Acknowledge last P3D.
|
|
while(REG_GX_PSC_STAT & 1u<<31) wait_cycles(0x30);
|
|
|
|
REG_GX_P3D(GPUREG_CMDBUF_SIZE0) = size>>3;
|
|
REG_GX_P3D(GPUREG_CMDBUF_ADDR0) = (u32)cmdList>>3;
|
|
REG_GX_P3D(GPUREG_CMDBUF_JUMP0) = 1;
|
|
}
|
|
|
|
// TODO: Sleep mode stuff needs some work.
|
|
/*void GFX_enterLowPowerState(void)
|
|
{
|
|
REG_LCD_ABL0_FILL = 1u<<24; // Force blackscreen
|
|
REG_LCD_ABL1_FILL = 1u<<24; // Force blackscreen
|
|
GFX_waitForEvent(GFX_EVENT_PDC0, true);
|
|
|
|
// Stop PDCs.
|
|
REG_LCD_PDC0_CNT = 0x700; // Stop
|
|
REG_LCD_PDC1_CNT = 0x700; // Stop
|
|
REG_LCD_PDC0_SWAP = 0x70100;
|
|
REG_LCD_PDC1_SWAP = 0x70100;
|
|
|
|
REG_GX_PSC_VRAM = 0xF00;
|
|
getPdnRegs()->gpu_cnt = PDN_GPU_CNT_NORST_ALL;
|
|
}
|
|
|
|
void GFX_returnFromLowPowerState(void)
|
|
{
|
|
getPdnRegs()->gpu_cnt = PDN_GPU_CNT_CLK_EN | PDN_GPU_CNT_NORST_ALL;
|
|
REG_GX_PSC_VRAM = 0;
|
|
//REG_GX_GPU_CLK = 0x70100;
|
|
REG_GX_PSC_FILL0_CNT = 0;
|
|
REG_GX_PSC_FILL1_CNT = 0;
|
|
// *((vu32*)0x10400050) = 0x22221200;
|
|
// *((vu32*)0x10400054) = 0xFF2;
|
|
|
|
setupDislayController(0);
|
|
setupDislayController(1);
|
|
const u32 swap = 0x70100 | g_gfxState.swap;
|
|
REG_LCD_PDC0_SWAP = swap;
|
|
REG_LCD_PDC1_SWAP = swap;
|
|
REG_LCD_PDC0_CNT = 0x10501; // Start
|
|
REG_LCD_PDC1_CNT = 0x10501; // Start
|
|
|
|
REG_LCD_ABL0_FILL = 0;
|
|
REG_LCD_ABL1_FILL = 0;
|
|
}*/
|