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225 lines
8.2 KiB
C
225 lines
8.2 KiB
C
/*
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* This file is part of open_agb_firm
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* Copyright (C) 2021 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "types.h"
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#include "arm11/drivers/gic.h"
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#include "arm11/drivers/interrupt.h"
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#include "mmio.h"
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#include "arm.h"
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#include "arm11/drivers/cfg11.h"
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// Level high active keeps firing until acknowledged (on the periphal side).
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// Rising edge sensitive only fires on rising edges.
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#define ICONF_RSVD (0u) // Unused/reserved.
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#define ICONF_L_NN (0u) // Level high active, N-N software model.
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#define ICONF_L_1N (1u) // Level high active, 1-N software model.
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#define ICONF_E_NN (2u) // Rising edge sinsitive, N-N software model.
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#define ICONF_E_1N (3u) // Rising edge sinsitive, 1-N software model.
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#define MAKE_ICONF(c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15) \
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((c15)<<30 | (c14)<<28 | (c13)<<26 | (c12)<<24 | (c11)<<22 | \
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(c10)<<20 | (c9)<<18 | (c8)<<16 | (c7)<<14 | (c6)<<12 | \
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(c5)<<10 | (c4)<<8 | (c3)<<6 | (c2)<<4 | (c1)<<2 | (c0))
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// First 32 interrupts are private to each core (4 * 32).
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// 96 external interrupts (total 128).
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IrqIsr g_irqIsrTable[224] = {0};
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// Per core interrupts.
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static void configPrivateInterrupts(Gicd *const gicd)
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{
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// Disable first 32 interrupts.
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// Interrupts 0-15 cant be disabled.
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gicd->enable_clear[0] = 0xFFFFFFFFu;
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// Set first 32 interrupts to inactive state.
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// Interrupt 0-15 can't be set to inactive.
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gicd->pending_clear[0] = 0xFFFFFFFFu;
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// Set first 32 interrupts to lowest priority.
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iomemset(gicd->pri, 0xF0F0F0F0u, 8 * 4);
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// Interrupt target 0-31 can't be changed.
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// Kernel11 config.
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// Interrupts 0-15.
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gicd->config[0] = MAKE_ICONF(ICONF_E_NN, ICONF_E_NN, ICONF_E_NN, ICONF_E_NN, // 0-3
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ICONF_E_NN, ICONF_E_NN, ICONF_E_NN, ICONF_E_NN, // 4-7
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ICONF_E_NN, ICONF_E_NN, ICONF_E_NN, ICONF_E_NN, // 8-11
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ICONF_E_NN, ICONF_E_NN, ICONF_E_NN, ICONF_E_NN); // 12-15
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// Interrupts 16-31.
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gicd->config[1] = MAKE_ICONF(ICONF_RSVD, ICONF_RSVD, ICONF_RSVD, ICONF_RSVD, // 16-19
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ICONF_RSVD, ICONF_RSVD, ICONF_RSVD, ICONF_RSVD, // 20-23
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ICONF_RSVD, ICONF_RSVD, ICONF_RSVD, ICONF_RSVD, // 24-27
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ICONF_RSVD, ICONF_E_NN, ICONF_E_NN, ICONF_RSVD); // 28-31
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}
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static void configExternalInterrupts(Gicd *const gicd)
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{
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// Kernel11 config with slight modifications.
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static const u32 configTable[6] =
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{
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// Interrupts 32-47.
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MAKE_ICONF(ICONF_L_1N, ICONF_L_1N, ICONF_L_1N, ICONF_L_1N, // 32-35
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ICONF_E_1N, ICONF_L_1N, ICONF_RSVD, ICONF_RSVD, // 36-39
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/*ICONF_L_1N, ICONF_L_1N, ICONF_L_1N, ICONF_L_1N, // 40-43
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ICONF_L_1N, ICONF_L_1N, ICONF_RSVD, ICONF_RSVD),*/ // 44-47
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ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, // 40-43 Modified to prevent IRQ storms.
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ICONF_E_1N, ICONF_E_1N, ICONF_RSVD, ICONF_RSVD), // 44-47 Modified to prevent IRQ storms.
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// Interrupts 48-63.
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MAKE_ICONF(ICONF_L_1N, ICONF_L_1N, ICONF_L_1N, ICONF_L_1N, // 48-51
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ICONF_L_1N, ICONF_L_1N, ICONF_L_1N, ICONF_L_1N, // 52-55
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ICONF_L_1N, ICONF_L_1N, ICONF_L_1N, ICONF_L_1N, // 56-59
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ICONF_RSVD, ICONF_RSVD, ICONF_RSVD, ICONF_RSVD), // 60-63
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// Interrupts 64-79.
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MAKE_ICONF(ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, // 64-67
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ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, ICONF_RSVD, // 68-71
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ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, // 72-75
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ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, ICONF_L_1N), // 76-79
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// Interrupts 80-95.
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MAKE_ICONF(ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, // 80-83
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ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, // 84-87
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ICONF_L_1N, ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, // 88-91
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ICONF_RSVD, ICONF_RSVD, ICONF_RSVD, ICONF_E_1N), // 92-95
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// Interrupts 96-111.
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MAKE_ICONF(ICONF_E_1N, ICONF_E_1N, ICONF_RSVD, ICONF_RSVD, // 96-99
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ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, ICONF_RSVD, // 100-103
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ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, // 104-107
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ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, ICONF_E_1N), // 108-111
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// Interrupts 112-127.
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MAKE_ICONF(ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, ICONF_E_1N, // 112-115
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ICONF_E_1N, ICONF_E_1N, ICONF_L_1N, ICONF_L_1N, // 116-119
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ICONF_E_1N, ICONF_L_1N, ICONF_L_1N, ICONF_L_1N, // 120-123
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ICONF_L_1N, ICONF_L_1N, ICONF_RSVD, ICONF_RSVD) // 124-127
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};
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iomemcpy(&gicd->config[2], configTable, 6 * 4);
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}
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// Note: Core 0 must execute this last.
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void IRQ_init(void)
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{
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Gicd *const gicd = getGicdRegs();
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gicd->ctrl = 0; // Disable the global interrupt distributor.
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configPrivateInterrupts(gicd);
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if(__getCpuId() == 0)
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{
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// Disable the remaining 96 interrupts.
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// Set the remaining 96 pending interrupts to inactive state.
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for(u32 i = 1; i < 4; i++)
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{
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gicd->enable_clear[i] = 0xFFFFFFFFu;
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gicd->pending_clear[i] = 0xFFFFFFFFu;
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}
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// Set the remaining 96 interrupts to lowest priority.
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// Set the remaining 96 interrupts to target no CPU.
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iomemset(&gicd->pri[8], 0xF0F0F0F0u, (32 - 8) * 4);
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iomemset(&gicd->target[8], 0, (32 - 8) * 4);
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configExternalInterrupts(gicd);
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// TODO: This is a potential bug. If any other core executes this
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// function the distributor will be disabled but not re-enabled.
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gicd->ctrl = 1; // Enable the global interrupt distributor.
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}
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Gicc *const gicc = getGiccRegs();
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gicc->primask = 0xF0; // Mask no interrupt.
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gicc->binpoint = 3; // All priority bits are compared for pre-emption.
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gicc->ctrl = 1; // Enable the interrupt interface for this CPU.
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getCfg11Regs()->fiq_mask = FIQ_MASK_CPU3 | FIQ_MASK_CPU2 | FIQ_MASK_CPU1 | FIQ_MASK_CPU0; // Disable FIQs.
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}
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void IRQ_registerIsr(Interrupt id, u8 prio, u8 cpuMask, IrqIsr isr)
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{
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const u32 cpuId = __getCpuId();
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if(!cpuMask) cpuMask = 1u<<cpuId;
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const u32 oldState = enterCriticalSection();
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g_irqIsrTable[(id < 32 ? 32 * cpuId + id : 96u + id)] = isr;
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// Priority
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Gicd *const gicd = getGicdRegs();
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const u32 idx = id / 4;
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u32 shift = (id % 4 * 8) + 4;
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u32 tmp = gicd->pri[idx] & ~(0xFu<<shift);
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gicd->pri[idx] = tmp | (u32)prio<<shift;
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// Target
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shift = id % 4 * 8;
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tmp = gicd->target[idx] & ~(0xFu<<shift);
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gicd->target[idx] = tmp | (u32)cpuMask<<shift;
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// Enable it.
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gicd->enable_set[id / 32] = 1u<<(id % 32);
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leaveCriticalSection(oldState);
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}
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void IRQ_enable(Interrupt id)
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{
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getGicdRegs()->enable_set[id / 32] = 1u<<(id % 32);
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}
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void IRQ_disable(Interrupt id)
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{
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getGicdRegs()->enable_clear[id / 32] = 1u<<(id % 32);
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}
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void IRQ_softInterrupt(Interrupt id, u8 cpuMask)
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{
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getGicdRegs()->softint = (u32)cpuMask<<16 | id;
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}
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void IRQ_setPriority(Interrupt id, u8 prio)
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{
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const u32 oldState = enterCriticalSection();
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Gicd *const gicd = getGicdRegs();
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const u32 idx = id / 4;
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const u32 shift = (id % 4 * 8) + 4;
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u32 tmp = gicd->pri[idx] & ~(0xFu<<shift);
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gicd->pri[idx] = tmp | (u32)prio<<shift;
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leaveCriticalSection(oldState);
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}
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// TODO: The reg write is atomic.
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// The ISR table write could be moved somewhere else by the compiler. Signal fence is enough?
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// Without critical section the ISR for this exact IRQ could re-enable it between the 2 writes.
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// Could be fixed by doing an acquire fence + doing the table write first.
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void IRQ_unregisterIsr(Interrupt id)
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{
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const u32 oldState = enterCriticalSection();
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getGicdRegs()->enable_clear[id / 32] = 1u<<(id % 32);
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g_irqIsrTable[(id < 32 ? 32 * __getCpuId() + id : 96u + id)] = (IrqIsr)NULL;
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leaveCriticalSection(oldState);
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}
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