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https://gitee.com/anod/open_agb_firm.git
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138 lines
4.9 KiB
C
138 lines
4.9 KiB
C
#pragma once
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/*
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* This file is part of libn3ds
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* Copyright (C) 2024 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "types.h"
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#include "mem_map.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#define CFG11_REGS_BASE (IO_COMMON_BASE + 0x40000)
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typedef struct
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{
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vu64 dsp_ram_code_cnt; // 0x000 8 u8 registers combined.
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vu64 dsp_ram_data_cnt; // 0x008 8 u8 registers combined.
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u8 _0x10[0xf0];
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vu32 nullpage_cnt; // 0x100
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vu8 fiq_mask; // 0x104
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vu8 unk105; // 0x105 Debug related? Mask?
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u8 _0x106[2];
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vu8 unk108; // 0x108 LGY gamecard related?
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u8 _0x109[3];
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vu8 cdma_cnt; // 0x10C
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u8 _0x10d[3];
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vu8 unk110; // 0x110 VRAM related?
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u8 _0x111[0x2f];
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vu16 gpuprot; // 0x140
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u8 _0x142[0x3e];
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vu8 wifi_power; // 0x180 Used for flight mode?
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u8 _0x181[0x3f];
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vu16 spi_cnt; // 0x1C0
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u8 _0x1c2[0x3e];
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vu32 unk200; // 0x200 GPIO3 related? 8x4 bits.
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u8 _0x204[0x1fc];
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vu8 gpu_n3ds_cnt; // 0x400 New3DS-only.
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u8 _0x401[0xf];
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vu32 cdma_peripherals; // 0x410 New3DS-only.
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u8 _0x414[0xc];
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vu8 bootrom_overlay_cnt; // 0x420 New3DS-only.
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u8 _0x421[3];
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vu32 bootrom_overlay_val; // 0x424 New3DS-only.
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vu8 unk428; // 0x429 New3DS-only. 1 bit. Enable CPU core 1 access to overlay regs?
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u8 _0x429[0xbd3];
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const vu16 socinfo; // 0xFFC
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} Cfg11;
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static_assert(offsetof(Cfg11, socinfo) == 0xFFC, "Error: Member socinfo of Cfg11 is not at offset 0xFFC!");
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ALWAYS_INLINE Cfg11* getCfg11Regs(void)
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{
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return (Cfg11*)CFG11_REGS_BASE;
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}
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// REG_DSP_RAM_CODE_CNT[8] and REG_DSP_RAM_DATA_CNT[8].
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// Note: All defines for each of the 8 registers.
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#define DSP_RAM_MASTER_ARM (0u) // Bank master CPU only.
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#define DSP_RAM_MASTER_DSP (1u) // Bank master DSP. The ARM CPUs still have access.
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#define DSP_RAM_OFFS(n) (((n) & 7u)<<2) // Bank offset in 32 KiB unit. 0-7.
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#define DSP_RAM_EN BIT(7) // Bank enable.
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// REG_CFG11_NULLPAGE_CNT
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#define NULLPAGE_CNT_FAULT_EN BIT(0) // All data accesses to 0x000-0xFFF generate data aborts.
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#define NULLPAGE_CNT_ACCESSED BIT(16) // 0x000-0xFFF has been accessed flag. Write 0 to clear.
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// REG_CFG11_FIQ_MASK
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// Each bit 1 = masked/disabled.
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#define FIQ_MASK_CPU0 BIT(0)
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#define FIQ_MASK_CPU1 BIT(1)
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#define FIQ_MASK_CPU2 BIT(2) // New3DS-only.
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#define FIQ_MASK_CPU3 BIT(3) // New3DS-only.
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// REG_CFG11_CDMA_CNT
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#define CDMA_CNT_MIC_EN BIT(0)
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#define CDMA_CNT_NTRCARD_EN BIT(1)
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#define CDMA_CNT_CAM1_EN BIT(2)
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#define CDMA_CNT_CAM2_EN BIT(3)
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#define CDMA_CNT_TMIO2_EN BIT(4) // WiFi
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#define CDMA_CNT_TMIO3_EN BIT(5)
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// REG_CFG11_GPUPROT
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// When the lower FCRAM protection is set to non-zero,
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// the first 0x800000 bytes of upper FCRAM are protected.
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#define GPUPROT_FCRAM_LO(x) (x) // Protect lower 128 MiB of FCRAM (0x28000000-(0x800000*x)).
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#define GPUPROT_FCRAM_UP(x) ((x)<<4) // Protect upper 128 MiB of FCRAM (0x30000000-(0x800000*x)) (New3DS-only).
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#define GPUPROT_AXIWRAM BIT(8) // Protect AXI RAM.
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#define GPUPROT_QTM(x) ((x)<<9) // Protect QTM RAM (0x1F400000-(0x100000*x)). 2 bits. TODO: Confirm this.
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#define GPUPROT_NO_PROT (0u)
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#define GPUPROT_PROT_ALL (GPUPROT_QTM(3u) | GPUPROT_AXIWRAM | \
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GPUPROT_FCRAM_UP(15u) | GPUPROT_FCRAM_LO(15u))
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// REG_CFG11_WIFI_POWER
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#define WIFI_POWER_ON BIT(0)
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// REG_CFG11_SPI_CNT
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#define SPI_CNT_SPI1_NEW_IF BIT(0) // New interface (NSPI).
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#define SPI_CNT_SPI2_NEW_IF BIT(1)
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#define SPI_CNT_SPI3_NEW_IF BIT(2)
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// REG_CFG11_GPU_N3DS_CNT
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#define GPU_N3DS_CNT_N3DS_MODE BIT(0) // Enable access to mem extensions.
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#define GPU_N3DS_CNT_TEX_FIX BIT(1) // Fixes some texture glitches in New3DS mode.
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// REG_CFG11_CDMA_PERIPHERALS
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// Each bit 1 = DMA requests go to CDMA2.
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// TODO: Add individual periphals.
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#define CDMA_PERIPHERALS_ALL (0x3FFFFu)
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// REG_CFG11_BOOTROM_OVERLAY_CNT
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#define BOOTROM_OVERLAY_CNT_EN BIT(0)
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// REG_CFG11_SOCINFO
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#define SOCINFO_CTR BIT(0) // Also set on New 3DS.
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#define SOCINFO_LGR1 BIT(1) // Never saw the daylight? Set on retail N3DS (LGR2).
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#define SOCINFO_LGR2 BIT(2) // Set on New 3DS.
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#ifdef __cplusplus
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} // extern "C"
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#endif |