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104 lines
5.0 KiB
C
104 lines
5.0 KiB
C
#pragma once
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/*
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* This file is part of libn3ds
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* Copyright (C) 2024 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "types.h"
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#include "mem_map.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#define SCU_REGS_BASE (MPCORE_PRIV_BASE)
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typedef struct
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{
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vu32 ctrl; // 0x00 SCU Control Register.
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const vu32 config; // 0x04 SCU Configuration Register.
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vu32 cpu_stat; // 0x08 SCU CPU Status Register.
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vu32 inval_all; // 0x0C SCU Invalidate All Register. (write-only)
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vu32 pmc; // 0x10 Performance Monitor Control Register.
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vu32 pme0; // 0x14 Performance monitor event register 0.
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vu32 pme1; // 0x18 Performance monitor event register 1.
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vu32 mn0; // 0x1C Count register 0.
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vu32 mn1; // 0x20 Count register 1.
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vu32 mn2; // 0x24 Count register 2.
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vu32 mn3; // 0x28 Count register 3.
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vu32 mn4; // 0x2C Count register 4. New 3DS only (4 CPUs).
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vu32 mn5; // 0x30 Count register 5. New 3DS only (4 CPUs).
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vu32 mn6; // 0x34 Count register 6. New 3DS only (4 CPUs).
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vu32 mn7; // 0x38 Count register 7. New 3DS only (4 CPUs).
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} Scu;
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static_assert(offsetof(Scu, mn7) == 0x38, "Error: Member mn7 of Scu is not at offset 0x38!");
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ALWAYS_INLINE Scu* getScuRegs(void)
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{
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return (Scu*)SCU_REGS_BASE;
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}
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// REG_SCU_CTRL
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#define SCU_EN BIT(0) // SCU is enabled, coherency is maintained between MP11 CPUs Level 1 data side caches.
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#define SCU_ACS(n) BIT((n) + 1) // CPUn can write to SCU-specific registers.
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#define SCU_INT_ALIAS_ACS(n) BIT((n) + 5) // CPUn can access aliased interrupt interface registers in the offset range 0x0200 to 0x050FF of the MPCore private memory region.
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#define SCU_TMR_ALIAS_ACS(n) BIT((n) + 9) // CPUn can access aliased timer and watchdog registers in the offset range 0x0700 to 0x0A0FF of the MPCore private memory region.
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#define SCU_PARITY_CHK_EN BIT(13) // SCU parity checking enable bit.
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#define SCU_CTRL_RST_VAL (SCU_TMR_ALIAS_ACS(3u) | SCU_TMR_ALIAS_ACS(2u) | \
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SCU_TMR_ALIAS_ACS(1u) | SCU_TMR_ALIAS_ACS(0u) | \
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SCU_INT_ALIAS_ACS(3u) | SCU_INT_ALIAS_ACS(2u) | \
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SCU_INT_ALIAS_ACS(1u) | SCU_INT_ALIAS_ACS(0u) | \
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SCU_ACS(3u) | SCU_ACS(2u) | SCU_ACS(1u) | SCU_ACS(0u))
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// REG_SCU_CONFIG
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#define SCU_CPU_NUM_1 (0u) // 1 MP11 CPU, CPU0.
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#define SCU_CPU_NUM_2 (1u) // 2 MP11 CPUs, CPU0-CPU1.
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#define SCU_CPU_NUM_3 (2u) // 3 MP11 CPUs, CPU0-CPU2.
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#define SCU_CPU_NUM_4 (3u) // 4 MP11 CPUs, CPU0-CPU3.
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#define SCU_CPU_NUM_MASK (SCU_CPU_NUM_4)
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#define SCU_SMP(n) BIT((n) + 4) // MP11 CPUn is in SMP mode taking part in coherency.
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#define SCU_TRAM_16KB_64I(n) (0u) // CPUn 16KB cache, 64 indexes per tag RAM.
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#define SCU_TRAM_32KB_128I(n) (1u<<((n) * 2 + 8)) // CPUn 32KB cache, 128 indexes per tag RAM.
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#define SCU_TRAM_64KB_256I(n) (2u<<((n) * 2 + 8)) // CPUn 64KB cache, 256 indexes per tag RAM.
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// REG_SCU_CPU_STAT
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#define SCU_STAT_NORMAL(n) (0u) // CPUn Normal mode (Default).
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// 1 reserved.
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#define SCU_STAT_DORMANT(n) (2u<<((n) * 2)) // CPUn is about to enter (or is in) dormant mode. No CCB request is sent to the CPU.
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#define SCU_STAT_PWROFF(n) (3u<<((n) * 2)) // CPUn is about to enter (or is in) powered-off mode, or is nonpresent. No CCB request is sent to the CPU.
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#define SCU_STAT_MASK(n) (SCU_STAT_PWROFF(n))
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// REG_SCU_INVAL_ALL
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#define SCU_WAY_0(n) (1u<<((n) * 4)) // CPUn invalidate way 0.
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#define SCU_WAY_1(n) (2u<<((n) * 4)) // CPUn invalidate way 1.
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#define SCU_WAY_2(n) (4u<<((n) * 4)) // CPUn invalidate way 2.
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#define SCU_WAY_3(n) (8u<<((n) * 4)) // CPUn invalidate way 3.
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#define SCU_WAY_ALL (SCU_WAY_3(3u) | SCU_WAY_2(3u) | SCU_WAY_1(3u) | \
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SCU_WAY_0(3u) | SCU_WAY_3(2u) | SCU_WAY_2(2u) | \
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SCU_WAY_1(2u) | SCU_WAY_0(2u) | SCU_WAY_3(1u) | \
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SCU_WAY_2(1u) | SCU_WAY_1(1u) | SCU_WAY_0(1u) | \
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SCU_WAY_3(0u) | SCU_WAY_2(0u) | SCU_WAY_1(0u) | \
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SCU_WAY_0(0u))
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// TODO: SCU performance monitor bits.
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#ifdef __cplusplus
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} // extern "C"
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#endif |