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https://gitee.com/anod/open_agb_firm.git
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78da297199
gfx: 常量大改名、函数大改名，增加了双缓冲的一些驱动函数 其他：基本是ARM9/ARM11宏修改和BIT取值修改，bool从c风格转成c++强类型风格等。sha.c使用了memory.h进行的改动(copy32)
107 lines
3.7 KiB
C
107 lines
3.7 KiB
C
#pragma once
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/*
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* This file is part of libn3ds
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* Copyright (C) 2024 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "types.h"
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#include "mem_map.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#ifdef __ARM9__
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#define PXI_REGS_BASE (IO_AHB_BASE + 0x8000)
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#elif __ARM11__
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#define PXI_REGS_BASE (IO_COMMON_BASE + 0x63000)
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#endif // #ifdef __ARM9__
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typedef struct
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{
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union
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{
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struct
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{
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vu8 sync_recvd; // 0x0 Received. Set by remote CPU via SENT.
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vu8 sync_sent; // 0x1 Write-only, sent.
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u8 _0x2;
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vu8 sync_irq; // 0x3
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};
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vu32 sync; // 0x0
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};
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vu32 cnt; // 0x4
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vu32 send; // 0x8 Send FIFO.
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const vu32 recv; // 0xC Receive FIFO.
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} Pxi;
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static_assert(offsetof(Pxi, recv) == 0xC, "Error: Member recv of Pxi is not at offset 0xC!");
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ALWAYS_INLINE Pxi* getPxiRegs(void)
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{
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return (Pxi*)PXI_REGS_BASE;
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}
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// REG_PXI_SYNC
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// Note: SENT and RECV in REG_PXI_SYNC do not count
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// the amount of bytes sent or received through the FIFOs!
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// They are simply CPU read-/writable fields.
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#define PXI_SYNC_RECVD (REG_PXI_SYNC & 0xFFu)
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#define PXI_SYNC_SENT(sent) ((REG_PXI_SYNC & ~(0xFFu<<8)) | (sent)<<8)
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#ifdef __ARM9__
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#define PXI_SYNC_IRQ BIT(29) // Trigger interrupt on ARM11.
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#define PXI_SYNC_IRQ2 BIT(30) // Another, separate interrupt trigger for ARM11.
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#elif __ARM11__
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// 29 unused unlike ARM9 side.
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#define PXI_SYNC_IRQ BIT(30) // Trigger interrupt on ARM9.
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#endif // #ifdef __ARM9__
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#define PXI_SYNC_IRQ_EN BIT(31) // Enable interrupt(s) from remote CPU.
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// REG_PXI_SYNC_IRQ (byte 3 of REG_PXI_SYNC)
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#ifdef __ARM9__
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#define PXI_SYNC_IRQ_IRQ BIT(5) // Trigger interrupt on ARM11.
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#define PXI_SYNC_IRQ_IRQ2 BIT(6) // Another, separate interrupt trigger for ARM11.
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#elif __ARM11__
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// 29 unused unlike ARM9 side.
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#define PXI_SYNC_IRQ_IRQ BIT(6) // Trigger interrupt on ARM9.
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#endif // #ifdef __ARM9__
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#define PXI_SYNC_IRQ_IRQ_EN BIT(7) // Enable interrupt(s) from remote CPU.
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// REG_PXI_CNT
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// Status bits: 0 = no, 1 = yes.
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#define PXI_CNT_SEND_EMPTY BIT(0) // Send FIFO empty status.
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#define PXI_CNT_SEND_FULL BIT(1) // Send FIFO full status.
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#define PXI_CNT_SEND_NOT_FULL_IRQ_EN BIT(2) // Send FIFO not full interrupt enable. TODO: Test the behavior.
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#define PXI_CNT_FLUSH_SEND BIT(3) // Flush send FIFO.
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#define PXI_CNT_RECV_EMPTY BIT(8) // Receive FIFO empty status.
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#define PXI_CNT_RECV_FULL BIT(9) // Receive FIFO full status.
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#define PXI_CNT_RECV_NOT_EMPTY_IRQ_EN BIT(10) // Receive FIFO not empty interrupt enable. TODO: Test the behavior.
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#define PXI_CNT_FIFO_ERROR BIT(14) // Receive FIFO underrun or send FIFO overrun error flag. Acknowledge by writing 1.
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#define PXI_CNT_EN_FIFOS BIT(15) // Enables REG_PXI_SEND and REG_PXI_RECV FIFOs.
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// All of the below functions for libn3ds internal usage only.
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void PXI_init(void);
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void PXI_deinit(void);
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u32 PXI_sendCmd(u32 cmd, const u32 *buf, u32 words);
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#ifdef __cplusplus
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} // extern "C"
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#endif |