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161 lines
4.4 KiB
ArmAsm
161 lines
4.4 KiB
ArmAsm
@ This file is part of libn3ds
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@ Copyright (C) 2024 derrek, profi200
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@
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@ This program is free software: you can redistribute it and/or modify
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@ it under the terms of the GNU General Public License as published by
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@ the Free Software Foundation, either version 3 of the License, or
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@ (at your option) any later version.
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@
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@ This program is distributed in the hope that it will be useful,
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@ but WITHOUT ANY WARRANTY; without even the implied warranty of
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@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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@ GNU General Public License for more details.
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@
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@ You should have received a copy of the GNU General Public License
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@ along with this program. If not, see <http://www.gnu.org/licenses/>.
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#include "asm_macros.h"
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.syntax unified
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.cpu arm946e-s
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.fpu softvfp
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.equ I_CACHE_SIZE, 0x2000
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.equ D_CACHE_SIZE, 0x1000
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.equ CACHE_LINE_SIZE, 32
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@ If a cache range operation is >= threshold do it on the whole cache.
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@ Whole cache invalidate is almost always faster (single instruction)
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@ but it's very hard to predict how badly this affects system performance
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@ so these are rough guesses at which point whole cache is overall cheaper.
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@ Flush may need adjustment too.
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.equ I_INVAL_THRESHOLD, 0x4800
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.equ D_INVAL_THRESHOLD, 0x3800
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.equ CLEAN_THRESHOLD, D_CACHE_SIZE
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.equ FLUSH_THRESHOLD, D_CACHE_SIZE
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BEGIN_ASM_FUNC invalidateICache
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ Flush instruction cache.
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC invalidateICacheRange
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cmp r1, #I_INVAL_THRESHOLD
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bhs invalidateICache
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add r1, r1, r0
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bic r0, r0, #CACHE_LINE_SIZE - 1
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invalidateICacheRange_lp:
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mcr p15, 0, r0, c7, c5, 1 @ Flush instruction cache single entry (address).
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add r0, r0, #CACHE_LINE_SIZE
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cmp r0, r1
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blo invalidateICacheRange_lp
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC invalidateDCache
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mov r0, #0
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mcr p15, 0, r0, c7, c6, 0 @ Flush data cache.
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC invalidateDCacheRange
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cmp r1, #D_INVAL_THRESHOLD
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bhs flushDCache
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tst r0, #CACHE_LINE_SIZE - 1
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add r1, r1, r0
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mcrne p15, 0, r0, c7, c10, 1 @ Clean data cache entry (address).
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tst r1, #CACHE_LINE_SIZE - 1
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bic r0, r0, #CACHE_LINE_SIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ Clean data cache entry (address).
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mov r2, #0
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invalidateDCacheRange_lp:
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mcr p15, 0, r0, c7, c6, 1 @ Flush data cache single entry (address).
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add r0, r0, #CACHE_LINE_SIZE
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cmp r0, r1
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blo invalidateDCacheRange_lp
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mcr p15, 0, r2, c7, c10, 4 @ Drain write buffer.
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC invalidateBothCaches
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ Flush instruction cache.
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mcr p15, 0, r0, c7, c6, 0 @ Flush data cache.
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC cleanDCache
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mov r1, #0
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cleanDCache_segment_lp:
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mov r0, r1 @ New segment. Reset index.
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cleanDCache_index_lp:
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mcr p15, 0, r0, c7, c10, 2 @ Clean data cache entry (index and segment).
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add r0, r0, #CACHE_LINE_SIZE @ Increment index.
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tst r0, #D_CACHE_SIZE / 4
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beq cleanDCache_index_lp
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adds r1, r1, #0x40000000 @ Increment segment.
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bne cleanDCache_segment_lp
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mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer.
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC cleanDCacheRange
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cmp r1, #CLEAN_THRESHOLD
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bhs cleanDCache
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add r1, r1, r0
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bic r0, r0, #CACHE_LINE_SIZE - 1
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mov r2, #0
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cleanDCacheRange_lp:
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mcr p15, 0, r0, c7, c10, 1 @ Clean data cache entry (address).
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add r0, r0, #CACHE_LINE_SIZE
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cmp r0, r1
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blo cleanDCacheRange_lp
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mcr p15, 0, r2, c7, c10, 4 @ Drain write buffer.
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC flushDCache
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mov r1, #0
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flushDCache_segment_lp:
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mov r0, r1 @ New segment. Reset index.
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flushDCache_index_lp:
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mcr p15, 0, r0, c7, c14, 2 @ Clean and flush data cache entry (index and segment).
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add r0, r0, #CACHE_LINE_SIZE @ Increment index.
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tst r0, #D_CACHE_SIZE / 4
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beq flushDCache_index_lp
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adds r1, r1, #0x40000000 @ Increment segment.
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bne flushDCache_segment_lp
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mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer.
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bx lr
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END_ASM_FUNC
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BEGIN_ASM_FUNC flushDCacheRange
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cmp r1, #FLUSH_THRESHOLD
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bhs flushDCache
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add r1, r1, r0
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bic r0, r0, #CACHE_LINE_SIZE - 1
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mov r2, #0
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flushDCacheRange_lp:
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mcr p15, 0, r0, c7, c14, 1 @ Clean and flush data cache entry (address).
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add r0, r0, #CACHE_LINE_SIZE
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cmp r0, r1
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blo flushDCacheRange_lp
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mcr p15, 0, r2, c7, c10, 4 @ Drain write buffer.
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bx lr
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END_ASM_FUNC |